IBM's PowerPC 405LP system-on-chip processor, which seems poised to compete with Intel's XScale processors for mobile device design wins, is described in its preliminary data sheet as a "highly integrated device offering high-performance at ultra-low power". The chip contains a 32-bit PowerPC 405D4 RISC core processor (with MMU) which dynamically scales from 152 to 380 MHz, and also includes an SDRAM/RAM/ROM/Flash controller, DMA and interrupt controllers, extensive power management, color LCD controller for 1/4 VGA up to XGA (2K x 2K pixels), touch panel interface, 2 16550-type serial ports, IIC (master and slave), CODEC interface, and up to 32 general purpose I/O lines. The 405LP implements a technology known as dynamic power management, for both processor and memory power requirements, in order to maximize battery life in mobile devices.