Apple to use HyperTransport?

[MacRumors]

CNet reports (http://news.com.com/2100-1042_3-1016770.html) that Apple Computer is planning to discuss their use of HyperTransport at WWDC:


The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.


According to the article, Hypertransport 1.0 allows for data transfer rates of "6.4 gigabytes to 12.8 gigabytes" (ed note: per second ?) and while definate ship dates for new computers are unclear, they expect that "it should not be too long" before the technology makes it into new Macs.

Based on recent rumors, Apple is widely expected to utilize the PowerPC 970 chip from IBM in future computers, and may discuss this technology at the WWDC.

[DHagan4755]

Things are starting to blossom from much more reliable news outlets.

[P-Worm]

I think that this is awesome. If Apple wants to get back in the race they are going to utilize the newest technology as quickly as possible.

P-Worm

[rice_web]

I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.

I'll try to dig up C|Net's previous foul-ups on Apple rumors.

[noverflow]

hmmm... I think this is in a way a bad thing. only because "it should not be too long" seems like it could mean that there will be a revision between now and when it is used.

[Freg3000]

Originally posted by rice_web
I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.

I'll try to dig up C|Net's previous foul-ups on Apple rumors.

You are probably right about cNet screwing up a couple of times, but for me, this is the most reliable source that we have gotten G5 info from. The sources of have gotten much more credible over the last few days. From MacB to MacWhispers to eWeek and now to cNet. :)

[seamuskrat]

This technology is nice. Its an interconnect with room to grow as the 970, 980 blossom.
This tech poses significant relevance to developers, so the WWDC WOULD be the place to discuss this.
So, following my rusty logic, if they discus hypertransport, then they let the cat out of the bag that new Macs are on the way. So it looks like they just may demo new stuff.
But I must still be a hard dose of reality and say that we are looking at early August at best for actually getting one of these in our hot little hands.

[GregGomer]

Thus the need for smeagol. Many people were so hung up on the new 10.2.7 code named smeagol enabling 64 bit functionalitly. But the 970s from what I understand do 32 bit natively, so no need for rewrites in software.

However, if you are using Hypertransport, and want to enable a new chipset. You need an OS that supports the new chips, and technology, thus the Smeagol. Just my take on it of course, but that makes more sense to me.

[reedm007]

Hey Arn--

I'm not sure if this would work out, and I don't want to cause any political tension between sites or anything, but it would be really helpful to have something like a "buyers guide" for rumor site reliabilities.

You could go through different rumor sites, their predictions, the reality of those predictions, and then how credible a source that rumor site is. That would be really useful in determining validity of different rumors?

Cheers,
ReeD.

[vitrector]

Newsfactor also has an article stating that Apple will be using Hypertransport (and an AMD chipset) in the forthcoming Powermas:
"According to preliminary reports -- completely unsubstantiated by Apple -- the G5 will be turbo-charged with IBM's (NYSE: IBM - news) 64-bit PPC 970 processor. The system's 64-bit addressing will be a major step past Apple's current bus architecture. The new machines will also include AMD's (NYSE: AMD - news) Hypertransport technology, which can push data down pipes at speeds in the neighborhood of 12.8 Gigabytes per second. "
For the complete article: http://story.news.yahoo.com/news?tmpl=story&u=/nf/20030612/bs_nf/21715

We'll see soon, I guess....

[Sun Baked]

I'm sooo glad these journalists know more than the gang at arstechnica, who are still trying to get info on exactly what type of bus IBM is using on the 970. :rolleyes:

Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.

Or are they just relying on bus speeds rates to say it's HT. :rolleyes:

Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.

---

Hannibal should be talking to the IBM PPC 970 architects sometime to get an idea of the SMP topology, and some of the nitty-gritty details answered. When is the question...

[ozubahn]

Do they really mean gigabytes ? 6.4 to 12.8 gigabytes/sec seems like too much (by, say, a factor of eight).

[markiv810]

This might appear to be off-topic, but are we going to be seeing the G5's (970's) soon or is it going to take a while for every mac user's dream to become a reality. How much is this dream machine going to cost, would it be replacing the entire PowerMac line.

[arn]

Originally posted by ozubahn
Do they really mean gigabytes ? 6.4 to 12.8 gigabytes/sec seems like too much (by, say, a factor of eight).

looks like it is gigabytes per second

http://www.hypertransport.org/faqs.html

arn

[noverflow]

Originally posted by ozubahn
Do they really mean gigabytes ? 6.4 to 12.8 gigabytes/sec seems like too much (by, say, a factor of eight).

It is gigabytes and not bits.
look at their page.

[cb911]

GregGomer, are you sure that the current version of Jaguar would operate OK on a 970? i thought that they had to release an update so that it would work on the 970's... but since they are backward-compatible with 32-bit apps i guess it does make sense that Smeagol would have all the HyperTransport tweaks.

saying that "it should not be too long" sounds like the first batch won't have HT technology... but they'll probably just discuss it at WWDC. this is very sudden news of Apple using HT, sounds like it'll be in the Rev. B 970 machines.

[technocoy]

SWEET JESUS!!! I Can't WAIT!!! down with WINTELS!!!!
My Guy at IBM told me the other day that IBM is using AMD alot anyway, and that they are going to be in their workstations and eServers...

Yipeeeeeee!!! bring on the 970s:D

[arn]

Originally posted by cb911
GregGomer, are you sure that the current version of Jaguar would operate OK on a 970? i thought that they had to release an update so that it would work on the 970's... but since they are backward-compatible with 32-bit apps i guess it does make sense that Smeagol would have all the HyperTransport tweaks.

saying that "it should not be too long" sounds like the first batch won't have HT technology... but they'll probably just discuss it at WWDC. this is very sudden news of Apple using HT, sounds like it'll be in the Rev. B 970 machines.

OS updates would be needed to support new motherboard technologies (such as hypertransport) but ALSO modified (slightly) to support the 970:

http://www.macrumors.com/pages/2002/10/20021015205024.shtml


According to the article, 32-bit PowerPC OS's simply need to support new data structures and interrupt handlers, but 32-bit PowerPC apps would run unchanged

[mathiasr]

Apple could use HyperTransport links on the motherboard instead of the PCI bus (and still keep PCI or PCI-X slots behind tunnel chips).

The PowerPC 970 does not host HT controllers that could be used to interconnect the CPUs.
My guess is that all the cache coherency spooping will be done by the chipset and Apple will stay with a dual SMP system.
Unless they have a quad or octo CPU Mac in mind moving from SMP to a more NUMA like architecture would only increase the cost of the whole computer since the PowerPC 970 has no build-in memory controller.

[WM.]

Just so everyone's clear on this, I interpret this to mean that HT will be used to connect the northbridge and the southbridge of the new Power Macs. In the current Power Macs, the northbridge is called U2 and the southbridge is called KeyLargo. To understand this a bit better, check out the current Power Mac G4's block diagram (and the rest of the architecture documentation) at developer.apple.com (http://developer.apple.com/techpubs/hardware/Developer_Notes/Macintosh_CPUs-G4/PowerMacG4/2Architecture/index.html).

So the weird 970 proprietary bus thing will replace the MaxBus, and HT will partially replace the PCI bus.

HTH
WM

[mathiasr]

Originally posted by Sun Baked
I'm sooo glad these journalists know more than the gang at arstechnica, who are still trying to get info on exactly what type of bus IBM is using on the 970. :rolleyes:

Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.

Or are they just relying on bus speeds rates to say it's HT. :rolleyes:

Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.
To my knowledge the 970 bus is based on the "elastic" POWER4 bus, it just went from 128 bits wide to 32 bits, I don't think IBM is part of the HT consortium.

http://www-3.ibm.com/chips/products/powerpc/newsletter/dec2002/newproductfocus2.html
"The PowerPC 970 implements an Elastic I/O processor interface bus..."

[Sun Baked]

Originally posted by mathiasr
To my knowledge the 970 bus is based on the "elastic" POWER4 bus, it just went from 128 bits wide to 32 bits, I don't think IBM is part of the HT consortium. They were on the RIO board, but that doesn't mean anything.

Hannibal should get a lot of the answers on the SMP topology, bus, cache snooping methods, etc. whenever he gets the meeting with the 970 people.

Of course if you have concrete info, spill your guts. ;)

[Mr.Hey]

BusinessWeek (http://www.businessweek.com/technology/cnet/stories/1016770.htm) quotes the same

[GregGomer]

Originally posted by cb911
GregGomer, are you sure that the current version of Jaguar would operate OK on a 970? i thought that they had to release an update so that it would work on the 970's... but since they are backward-compatible with 32-bit apps i guess it does make sense that Smeagol would have all the HyperTransport tweaks.

Yah, I'm not in a position to be sure, I'm just speculating from what I've read. But it's my understanding that some upcoming 64 bit chips run 32 bit Apps in a type of emulation, where the IBM chip handles the 32 stuff natively. As to the current Jag working with the 970, probably not, as Arn said, you gotta have some drivers and support in their for the new AMD chipset, Hypertrasnport and the 970. So they'd need the new Jag release to add these few items. But it's my impression that yah, the 970 can run a 32 bit OS and apps just fine.

Now, here's my question, I've seen a few posts saying, dang, we won't see hypertransport till the rev B. I didn't see anything about the HT not being immediately available in the article, so where are we getting that it won't be available with the initial new machines.

Also, is AMD, Apple And nVidia are all on the HT consortium right. So is Hypertransport part of the nForce chipset used with so many AMD motherboards, or is it a completely different and new technology?

Thanks in advance for the info---

[unreg]

As I recall, RIO is one of the proposed PCI replacement technologies. Machines can have both Hypertransport and RapidIO.

[cb911]

i think that HT is a relatively new technology. having a quick look around the HT.org site it looks like only the NVIDIA nForce 3 Pro and the AMD Opteron are the only ones to use this technology in computing. not sure about this, but it looks like IBM (and then Apple) might be the first to use it.

i guess that the first 970's could have HT... if Smeagol is released will apps like Photoshop 7 etc be able to run on a HT 970? if the OS needs a slight change to operate properly, won't that mean that all apps will also need an update to be able to run on a HyperTransport 970?

this is just getting more and more complicated...

[mathiasr]

Originally posted by Sun Baked
Hannibal should get a lot of the answers on the SMP topology, bus, cache snooping methods, etc. whenever he gets the meeting with the 970 people.
Will he attend to the Westford Design Forum?
https://www-914.ibm.com/events/micro/03microcust.nsf

This session should be enlightenting:
Future Directions, 64-bit Multi-Gigahertz Embedded PowerPC's
by Jim Rogers, Senior Engineer PowerPC Products

Driven by ever increasing requirements for additional networked bandwidth combined with the ability to handle new and even more complex software and services the PowerPC® architecture is changing. To meet these challenges, and provide the best price/performance solution, a variety of enhancements to the Embedded PowerPC architecture are being implemented and include an extension into 64 bit computing, highly scalable Multi-Gigahertz frequency capability, advanced power management, instruction level parallelism, thread level parallelism and SIMD acceleration. In this session, these enhancements to the PowerPC® architecture will be reviewed, highlighting the improved capabilities of PowerPC technology and the benefits to embedded solutions.

[GregGomer]

Originally posted by unreg
As I recall, RIO is one of the proposed PCI replacement technologies. Machines can have both Hypertransport and RapidIO.

Wouldn't surprise me at all if the two do end up coexisting in some way.

From the looks of things though, rapidIO is aimed at the embeded market. I.e. things that are less software dependant and more hardware dependant. Like switches and routers etc. And as you look at the members on the consortium for RapidIO, you see it is mainly manufactures of Embeded products.

Here is a quote from www.rapidio.org

Q: What is the RapidIO interconnect target market?



A: The RapidIO interconnect is primarily targeted at the networking market. Unlike other contemporary computer-centric interconnects, the RapidIO technology addresses the networking industry's needs for software transparency, greater reliability, and higher bandwidth in an "in-the-box interconnect." The RapidIO interconnect provides higher bus speeds that allow chip-to-chip and board-to-board communications at performance levels scaling greater than ten gigabits per second.

----------------------------------------

As to the question above about will Apps like Photoshop have to be rewritten for them to work on a 970 machine. My understanding is NO. The 970's are inherently backwards compatible, and as such, they will run PhotoShop and other 32 bit apps as is. However, that doesn't mean that Photoshop can't be tweaked or updated to become a 64 bit app and take full advantage of the 64 bit processing power.

Kind of like the G3. When the G4 came out with Altivec/Velocity Engine, older versions of Photoshop ran just fine on the G3. But in time, Photoshop was updated to be able to take advantage of the G4 Velocity engine. As such it ran much faster on a G4, but was still compatible and still ran on a G3.

[mathiasr]

Originally posted by cb911
i guess that the first 970's could have HT... if Smeagol is released will apps like Photoshop 7 etc be able to run on a HT 970? if the OS needs a slight change to operate properly, won't that mean that all apps will also need an update to be able to run on a HyperTransport 970?
It should be entirely transparent... unless Apple shifts to a NUMA architecture where apps would have to avoid storing to much data in remote location memory, since each CPU would have local (fast) and remote (some what slower, remote is indeed local to another CPU) memory.
In an SMP design memory has always the same access time (as long the bus is not saturated).

[Sun Baked]

Originally posted by mathiasr
Will he attend to the Westford Design Forum?
https://www-914.ibm.com/events/micro/03microcust.nsf

This session should be enlightenting:
Future Directions, 64-bit Multi-Gigahertz Embedded PowerPC's
by Jim Rogers, Senior Engineer PowerPC Products Don't know, hopefully if he doesn't make it somebody else will.

Future CPU Thread (http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=8300945231&m=3470943335)

Check page 69 on...

[macFanDave]

and rename it the Gigahertz Guile.

It WAS true a few years ago. AMD gave it legitimacy when it stopped using clock speeds and named processor chips for the Pentium equivalent performance. Even Intel themselves have been forced to accept the truth of the Megahertz Myth to explain why Itanium chips have slower clock speeds than Pentiums.

However, with Motorola's slovenliness (and Apple's lack of progress with motherboard architecture), the clock speed gap has become so vast that the "Myth" logic is overwhelmed.

I work on a fast Windows box during the day and still prefer working at home on Macs with a fraction of the clock speed.

Nevertheless, I think it would be great if Apple could regain superior (or at least comparable) performance for those who really focus on that. If it causes some of us using older Macs to upgrade, it would be an excellent business move. If it also gets a non-trivial number of switchers, it will be brilliant!

[DeusOmnis]

apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.

[Mudbug]

Originally posted by DeusOmnis
apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.
but maybe (hopefully) they're trying to change that outlook, and this seems like the best chance to do it with. New hotness processor plus new hotness hyperthreading = old and busted wintel machines.
I like the idea of winning a power contest by factors of numbers, not just numbers. But in the end, I just want to go faster. Soon.

[IJ Reilly]

Originally posted by vitrector
Newsfactor also has an article stating that Apple will be using Hypertransport (and an AMD chipset) in the forthcoming Powermas:
"According to preliminary reports -- completely unsubstantiated by Apple -- the G5 will be turbo-charged with IBM's (NYSE: IBM - news) 64-bit PPC 970 processor. The system's 64-bit addressing will be a major step past Apple's current bus architecture. The new machines will also include AMD's (NYSE: AMD - news) Hypertransport technology, which can push data down pipes at speeds in the neighborhood of 12.8 Gigabytes per second. "

This is just another one of those "OSOpinions" columns, where they give a big soap-box to a clueless person and let them embarrass themselves royally in front of lots of people. It's some kind of entertainment, anyway.

Just look at the quote, "the G5 will be turbo-charged with IBM's 64-bit PPC 970 processor." This statement doesn't even makes sense.

[cb911]

this is all really confusing to me now. HT may or may not be in the 970, but i'll just have to wait till i can get my hands on one to understand it better. :D


edit>> i just checked and found out that Apple Computer is a member of the HyperTransport™ Technology Consortium. interesting. i guess that almost guarantees that Apple will use HT sometime in the future.

[Cappy]

Originally posted by DeusOmnis
apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.

You're correct most of their record has been one of catching up but word on the street is that things are changing. Maybe not right away but they're certainly making some changes for the better.

[Cappy]

Folks, I'm interpretting alot of misinformation here on what HT really is. Read up on it if you're interested. I'm certainly not an expert on it enough to describe it and give it justice but much of what I've seen here hasn't been too accurate. Remember there are many buses in a computer. The pci bus is not all there is to a computer and HT certainly is not replacing it.

[mim]

Originally posted by DeusOmnis
apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.

Well, recent record. But this is hardly true for Apple's total record.

I see no reason to be pessimistic. One reson we may not have seen Apple's recent hardware advancing as fast as their software is that their engineers have been beavering away on some mighty big projects for the past two years....

[3.1416]

Originally posted by DeusOmnis
apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.

There's no reason to believe that Apple is doomed to always lag behind Wintel. From the introduction of the PowerPC through the G3, Macs were very competitive performance-wise. The current problems are the exception, not the rule.

[pgwalsh]

Originally posted by seamuskrat

So, following my rusty logic, if they discus hypertransport, then they let the cat out of the bag that new Macs are on the way. So it looks like they just may demo new stuff.
Someone please help us if they're not. It's more of a question as to when they will arrive and what they'll have in them... We know they're coming.

[Frobozz]

Interestingly, this seems to indicate that at least one dual processor config will be available. So the question remains: is it only the high end, the high aend and middle end, or all three?

[Frobozz]

Originally posted by Cappy
Folks, I'm interpretting alot of misinformation here on what HT really is. Read up on it if you're interested. I'm certainly not an expert on it enough to describe it and give it justice but much of what I've seen here hasn't been too accurate. Remember there are many buses in a computer. The pci bus is not all there is to a computer and HT certainly is not replacing it.

From what I understand the external busses, such as PCI and AGP, will obviously be the same. HyperTransport is a technology to get all the interconnects between chips on the motherboard to work on the same protocol and standard. This way, there is no translation problems when you move between processors, or from processors to memory, or from system controller to processor, etc.

My interpretation could be wrong, but I think that's the basics.

[jcdenton]

Originally posted by reedm007
Hey Arn--

I'm not sure if this would work out, and I don't want to cause any political tension between sites or anything, but it would be really helpful to have something like a "buyers guide" for rumor site reliabilities.

You could go through different rumor sites, their predictions, the reality of those predictions, and then how credible a source that rumor site is. That would be really useful in determining validity of different rumors?

Cheers,
ReeD.


Try here: http://arrca.da.ru

I can't vouch entirely for the reliability of this site. I know the person putting it up and he isn't exactly the brightest person I know but, hey, it can't take too much to do this.

What he's working on is putting up lists of rumors posted by rumors sites, indexed only when they come from that site's own sources (that is, if MacRumors says ThinkSecret says XY, he only puts it up as a ThinkSecret rumor). He tells me he's working back to the beginning of 2003 and then up to the present. Each rumor gets tagged as either false or confirmed once its predictions are either staledated, proven wrong, or turn out to be right.

Not sure if that helps any but I've looked at it a couple times and it's better than nothing, even if it is still under construction.

[Frobozz]

Originally posted by IJ Reilly
This is just another one of those "OSOpinions" columns, where they give a big soap-box to a clueless person and let them embarrass themselves royally in front of lots of people. It's some kind of entertainment, anyway.

Just look at the quote, "the G5 will be turbo-charged with IBM's 64-bit PPC 970 processor." This statement doesn't even makes sense.

The quote makes sense. The G5 they are referring to is the Computer, not a CPU. The Moto G5 was an PowerPC 85xx. The IBM G5 is going to be a PowerPC 970. Again, the G5 is what Apple will brand the computer as, not the chip. Imagine a statement by Apple such as "The all-new Macintosh G5 incorporates IBM's ultra-fast PowerPC 970 chip."

[wizard]

Hi guys;

Lets just imagine that Apple is going with HyperTransport, whats to prevent them from producing a dual processor machine with one CPU that happens to be an AMD Opterion or what ever they call it. Imagine the marketing possibilities, especially if they where to have a MS operating slaved as a task under OSX!!

Lets face it the 970 is a given, the only quesiton is when. My suspision is that it is farther off then we would like. At least from the standpoint of a full implementation. The only thing to question is what Motorola may have up its sleeve to fill in the lines that may not migrate to the 970 off the bat.

Thanks
Dave

[bertagert]

Look at me doing the chicken dance...cluck, cluck...chicken dance!!!

People the new G5 (or whatever its called) is coming to a store near you real soon.

As for the HT thing...I would love to see it in the new ones but may have to wait but maybe not...

Now doing the funky chicken dance...cluck, cluck, cluck...

[GeeYouEye]

Originally posted by wizard
Hi guys;

Lets just imagine that Apple is going with HyperTransport, whats to prevent them from producing a dual processor machine with one CPU that happens to be an AMD Opterion or what ever they call it. Imagine the marketing possibilities, especially if they where to have a MS operating slaved as a task under OSX!!

Lets face it the 970 is a given, the only quesiton is when. My suspision is that it is farther off then we would like. At least from the standpoint of a full implementation. The only thing to question is what Motorola may have up its sleeve to fill in the lines that may not migrate to the 970 off the bat.

Thanks
Dave

À la the 486 they put in the 6100... yes... I could see that happening... that could be quite useful...

[herocero]

Originally posted by DeusOmnis
apple's record makes it such that we'll see this technology in the 990s, dont expect to see it soon, or anytime when it would be compedative in the pc market.

Originally posted by Mudbug
but maybe (hopefully) they're trying to change that outlook, and this seems like the best chance to do it with. New hotness processor plus new hotness hyperthreading = old and busted wintel machines.
I like the idea of winning a power contest by factors of numbers, not just numbers. But in the end, I just want to go faster. Soon.

This is the problem when you are playing with stacked cards, is that the one on top always has a killer waiting for you no matter what you do. Remember when AMD was trying to make huge strides into intel market share with price drops on k5's or whatever they were? what did intel do? they had the clout and ability to make even bigger price drops and introduce higher clocked chips . . . and no one saw it coming. i would love ht 970s too, but you gotta save your aces for the future too . . . until then we all get to be whiny and pratice our lack of patience :)

[RazorMouse]

In HyperTransport servers, the central bus is eliminated. Instead, processors and memory are spread out and united by a high-speed ring road, similar to the decentralized live-work areas that have become common in high-population areas.

Smeagol is the creature's old feeble self, awed and cowed by the power of the Ring, but represents the nicer, softer side. Gollum, however, is the shadow side, entirely in symbiosis with the Ring (enslaved by it).

10 cents on Panther being 'Gollum'?

[MOFS]

Found his link here at www.macworld.co.uk/news/top_news_item.cfm?NewsID=6446 Note that one of the technicians says Mac fans "will not be disappointed". Since the PPC 970 seems to be the only chip capable of (a) being out by WWDC and (b) not disapointing us, I think its a fair bet we'll see PPC 970 enabled Macs at WWDC 2003!

Waat!:p

[Jeff Harrell]

Originally posted by mathiasr
It should be entirely transparent... unless Apple shifts to a NUMA architecture where apps would have to avoid storing to much data in remote location memory, since each CPU would have local (fast) and remote (some what slower, remote is indeed local to another CPU) memory.
In an SMP design memory has always the same access time (as long the bus is not saturated). CC-NUMA is programmer-transparent, too. A NUMA system typically has a scheduler that knows how to migrate pages from node to node and that understands processor affinity. So the program doesn't have to worry about memory allocation at the hardware level at all, except in the very most extreme cases.

In other words, if you start a process on processor 12, that process is generally going to stay running on processor 12, even after dropping out of the run queue for things like blocking I/O. That's processor affinity.

When a process running on processor 12 allocates a block of memory, the system allocates that memory in the closest bank of RAM, topologically speaking. If that's not on the local node, then the system will page-migrate the memory to the local node as local RAM becomes available. This happens completely invisibly from the perspective of the application.

Now, NUMA systems are designed in multi-dimensional cube topologies, which means that even in a thousand-processor system a processor is never more than seven router hops away from the furthest bank of memory. In a 1,024-processor SGI Origin 3000 system like NASA's Chapman, for example, the average memory latency is 480 ns and the worst-case memory latency is only 640 ns. Best-case latency is 170 ns. So the total variance from best-case to worst-case is only about 3.7. And that's across a thousand processors. Oh, also that's with standard memory modules. And remember this is CPU-to-main-memory. In the real world, latencies are much lower thanks to fat caches and predictive fetching. Particularly in sequential-read applications like video processing for example (read a byte, write a byte; or read a vector, write a vector), the vast majority of the time the cache line that the processor reaches for next has already been loaded into cache predictively, so sequential applications are very cache-friendly.

For comparison, the round-trip time to main memory in a Power Mac G4 is about 95 ns. Throw a NUMA memory controller in there, and you would see memory latencies pretty much in line with the fastest computers in the world, give or take a few percent. In other words, you would NOT have to worry about local versus remote memory.

Now, in HPC/TC applications, programmers can directly manipulate the memory topology of a NUMA system to suit their needs. They can allocate given blocks of memory on given nodes if they so choose. That kind of application tuning is saved for the sort of long-running jobs where tweaking the memory allocations might save you a week or two of computer time over the course of the run. You won't see that kind of optimization on anything less than a supercomputer for a long, long time, because it just won't be worth it. Hand-coding the memory handling in a NUMA version of After Effects might save you three minutes over the course of a year. Hardly worth the effort.

Now, none of this means anything, except this: if Apple were to decide to implement small-scale NUMA (< 16 processors) using chips that are instruction-set compatible with the PowerPC G4 family, it would not be necessary for application vendors to go back and change their code to run on the new systems.

[Hattig]

Originally posted by cb911
i think that HT is a relatively new technology. having a quick look around the HT.org site it looks like only the NVIDIA nForce 3 Pro and the AMD Opteron are the only ones to use this technology in computing. not sure about this, but it looks like IBM (and then Apple) might be the first to use it.

i guess that the first 970's could have HT... if Smeagol is released will apps like Photoshop 7 etc be able to run on a HT 970? if the OS needs a slight change to operate properly, won't that mean that all apps will also need an update to be able to run on a HyperTransport 970?


HyperTransport is used in the XBox between the graphics processor and the I/O controller.

It is also used in the nForce, nForce2 and nForce3 chipsets for various AMD processors.

AFAIK HT doesn't need drivers, it works transparently to the operating system. Any changes being made to 32-bit MacOS will be adding drivers, etc, for other system components that are new on the new platform.

[Bengt77]

Originally posted by jcdenton


Deus Ex is my favourite game; it sooooooooo rules!

:D

[COS]

Hypertransport as I understand it does not necessarily need to be used throughout the system. I can see where they'd use it to connect the two processors in a dual chip computer but let the front-side bus be something different.

Though it is interesting that they picked the name "Smeagol" for the OS revision that allows thee 970 to be compatible, because the whole idea behind HT is to allow all the chips to speak the same language so nothing has to be translated from chip to chip. "One bus to bind them" perhaps?

[SpamJunkie]

Originally posted by COS
Though it is interesting that they picked the name "Smeagol" for the OS revision that allows thee 970 to be compatible, because the whole idea behind HT is to allow all the chips to speak the same language so nothing has to be translated from chip to chip. "One bus to bind them" perhaps?

Can we all drop the Smeagol speculation? They named it Smeagol because they are, surprise surprise, fans of LOTR. End of Story. The people at Apple don't have the time to waste thinking of clever code names for everything.

[macphisto]

Also, with cnet reporting the use of HT in Apple's new hardware, http://zdnet.com.com/2100-1103_2-1016770.html, ZDNet is also reporting that Apple will be adopting it as well.

"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.

The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer."

[Sun Baked]

Originally posted by macphisto
Also, with cnet reporting the use of HT in Apple's new hardware, http://zdnet.com.com/2100-1103_2-1016770.html, ZDNet is also reporting that Apple will be adopting it as well.

"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.

The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer." That is the SAME article...

It's getting reprinted everywhere in all the parent company's publications.

---

Confirmation from several sources using the same article. http://forums.macrumors.com/attachment.php?s=&postid=380969

[eric_n_dfw]

Originally posted by SpamJunkie
Can we all drop the Smeagol speculation? They named it Smeagol because they are, surprise surprise, fans of LOTR. End of Story. The people at Apple don't have the time to waste thinking of clever code names for everything. (Like normal, I'm veering way off topic here! Sorry Arn!)

These things usually do have some kind of meaning to someone. Whether it's a personal idea of one person or a marketting idea that sounds, well, marketable (Jaguar).

I worked at one place that named a release SkyLine - it was a reference, so I'm told, to a "line in the sky" of a sky high dream of how great the product would be. (yawn). The precursor to it was BARPH. Looked like an acronym but it actually was named that so that marketting would keep their mitt's off of it and not talk about it with customers!

Another company named their pre-releases of a new version of their software after various bridges in Portland, OR because: A.) That's where we worked and B.) They were "bridges" to new the new platform

My favorite one (to hate that is) was when I worked on a system for a large airline here in DFW. Our company (and the airline's), at the time, had a bunch of cool sounding code names like: ASP, T-REX, VIPER, Raptor, etc. Almost all were acronyms of some sort, so then the airline comes up with this new reservations platform and the code name is: AACoRN. I forget what the C and N stood for (the R was reservations - you can guess what airline AA was for ;) ) What a wussy name! The funniest part was arround the same time, the TV Dilbert show was airing and they had an episode where Dilbert was trying to come up with a code name so bad that the project he was on would get cancelled. What did he come up with? Acorn! We all had a big laugh about that!

So, yet again, what were we talking about? Oh yeah, I'll bet that by the time 10.3 is in the stores, we'll all 'get' what Smeagol meant and it'll probably be rather geek-cool.
:cool:

[ddtlm]

Jeff Harrell:

For comparison, the round-trip time to main memory in a Power Mac G4 is about 95 ns.
I'm very interested in knowing what version of PMac this is for, and what your source is.

COS:

Hypertransport as I understand it does not necessarily need to be used throughout the system. I can see where they'd use it to connect the two processors in a dual chip computer but let the front-side bus be something different.
The processors have to have pins+hardware supporting the HT link of course, which the PPC970 apparently does not have. Perhaps the PPC980 will use HT for interprocessor communication.

[mathiasr]

Originally posted by ddtlm
Jeff Harrell:I'm very interested in knowing what version of PMac this is for, and what your source is.
This could be mesured, trash all the caches, read the lower part of the time base, do a load followed by an isync, read the lower part of the time base again.

[ddtlm]

mathiasr:

I'm not a fan of making measurements like that myself. Seems like there's always something overlooked.

[Jeff Harrell]

Originally posted by ddtlm
Jeff Harrell: I'm very interested in knowing what version of PMac this is for, and what your source is. Got it from the Power Mac Technology Overview, January 2003, page 9. It's certainly available on the Apple site somewhere, but I'm looking at a PDF right now.

The table in question compares latency to main memory in the G4 to an unspecified 3 GHz P4 system with 20K of L1 cache and 512K of L2 cache and no L3 cache. The G4 reference system was a dual 1.42 with 64K L1, 256K L2, and 2 MB L3. It's divided up into L1 cache miss latency, L2 cache miss latency, L3 cache miss latency, and total time to main memory.

L1:
G4: 5 ns
P4: 10.1 ns

L2:
G4: 23.3 ns
P4: 135.8 ns

L3:
G4: 64.1 ns
P4: n/a

MM:
G4: 94.5 ns
P4: 146.6 ns

Thanks for calling me on it. I should have cited my sources. (The sources for the SGI numbers all come from techpubs.sgi.com, in various places. FYI.)

[ddtlm]

Jeff Harrell:

I wasn't calling you on it so much as looking for more information. I have found the Developer Note from March 14, 2003 at Apple's site but not the document you have. I'll keep looking around.

In other news, I just noticed in the developer's note that they do state the L3 cache speeds: 250mhz for 1.0ghz and 1.25ghz machines, 236mhz for the 1.42ghz Mac. I figured that they were doing that but hadn't ever seen it printed anywhere.

[mathiasr]

Originally posted by Jeff Harrell
Got it from the Power Mac Technology Overview, January 2003, page 9. It's certainly available on the Apple site somewhere, but I'm looking at a PDF right now.

The table in question compares latency to main memory in the G4 to an unspecified 3 GHz P4 system with 20K of L1 cache and 512K of L2 cache and no L3 cache. The G4 reference system was a dual 1.42 with 64K L1, 256K L2, and 2 MB L3. It's divided up into L1 cache miss latency, L2 cache miss latency, L3 cache miss latency, and total time to main memory.

L1:
G4: 5 ns
P4: 10.1 ns

L2:
G4: 23.3 ns
P4: 135.8 ns

L3:
G4: 64.1 ns
P4: n/a

MM:
G4: 94.5 ns
P4: 146.6 ns
It's available here:
http://www.apple.com/powermac/pdf/PowerMac_TO_012003.pdf

I'm trying to figure out what these figures actually mean... Why the hell do they provide miss latency and not hit latency?
Why don't they show:
L1 hit (3 or 4 cycles, 3 is for GPR, 4 is for FPR and VR)
L1 miss, L2 hit (9 cycles)
L1-L2 miss, L3 hit (more than 33 cycles depends on L3 config, 33 is for 4:1 frequency ratio, DDR L3 bus, 5 and 0 sample points, which is not the case on a 1.42 GHz machine)
L1-L3 miss, main memory access

[edit]
I've found the "Calibrator" tool they used to produce the figures:
http://homepages.cwi.nl/~manegold/Calibrator/calibrator.shtml

[WM.]

Originally posted by Cappy
Folks, I'm interpretting alot of misinformation here on what HT really is. Read up on it if you're interested. I'm certainly not an expert on it enough to describe it and give it justice but much of what I've seen here hasn't been too accurate. Remember there are many buses in a computer. The pci bus is not all there is to a computer and HT certainly is not replacing it.

If you're referring to my post, I didn't say that HT would replace PCI--of course any Power Mac would have to have some form of PCI to be practical. I said that HT would *partially* replace PCI, which is true.

HTH
WM

[mathiasr]

Originally posted by ddtlm
In other news, I just noticed in the developer's note that they do state the L3 cache speeds: 250mhz for 1.0ghz and 1.25ghz machines, 236mhz for the 1.42ghz Mac. I figured that they were doing that but hadn't ever seen it printed anywhere.
It suppose that SRAM ships running at more than 250 MHz would have been to expensive.
The L3 memory frenquency is linked to the CPU frequency, it is divided by a integer factor.
1.00 GHz divided by 4 gives 250 MHz
1.25 GHz divided by 5 gives 250 MHz
1.42 GHz divided by 6 gives 236 MHz

[mathiasr]

Originally posted by WM.
If you're referring to my post, I didn't say that HT would replace PCI--of course any Power Mac would have to have some form of PCI to be practical. I said that HT would *partially* replace PCI, which is true.
The PCI bus whipout is a reality, AMD has kept PCI slots behind the HT I/O hub (that offers a PCI bus) and PCI-X tunnels, but all the main chips on the motherboard are connected by HyperTransport. The PCI bus is history (it has become too slow) it's no more at the center of the motherboard, HT is logicaly compatible with PCI (wires are gone but software stays the same).

http://www.amdboard.com/opteron_chipsets_amd.html

"HyperTransport technology is the primary bus used in the AMD Athlon 64 and AMD Opteron processors and inside its supporting devices including the AMD-8111 HyperTransport I/O hub, the AMD-8131 HyperTransport PCI-X tunnel and the AMD-8151 HyperTransport AGP 3.0 graphics tunnel."

http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_5707_5733~62571,00.html

[WM.]

Originally posted by mathiasr
The PCI bus whipout is a reality, AMD has kept PCI slots behind the HT I/O hub (that offers a PCI bus) and PCI-X tunnels, but all the main chips on the motherboard are connected by HyperTransport. The PCI bus is history (it has become too slow) it's no more at the center of the motherboard, HT is logicaly compatible with PCI (wires are gone but software stays the same).
Right. I think we're on the same page. :)

WM

[AidenShaw]

Originally posted by mathiasr
[B]The PCI bus is history (it has become too slow) it's no more at the center of the motherboard, HT is logicaly compatible with PCI (wires are gone but software stays the same).

But, isn't this a bit obvious?

Although the PCI bus is "history", what I/O cards are you going to use? PCI, of course.

Systems haven't used the PCI bus as the "main bus" for a long time - it's a peripheral bus. The Intel 7505 chipset for Xeon DP has up to six PCI-X (133MHz) busses coming out of the north bridge. (Not six slots, six 64-bit 133MHz PCI busses.)

HT is good - it's a cheaper way of moving lots of data around (and even better, it's a cheaper way for moving modest amounts of data around). But, it doesn't bring anything revolutionary to the finished product.

You can have several 1GB/sec PCI-X busses on a 7505. You can do the same with HT. You may be able to come in faster and cheaper with HT (since you don't need 64-bit wide traces on the mobo), but it's not revolutionary.

Before you wet yourself over what Apple may be doing, check out the Intel mobos to see what's already available at a reasonable price. If you want to see what's possible (without worrying too much about the price), look at the IBM Summit chipset.

I'm not saying that HT and the 970 rumours are bunk - but even the most extravagant stories don't do much more than put Apple "back in the ballgame". On the Intel side many of these innovations are already in the stores, and on people's desks.

[hacurio1]

Originally posted by rice_web
I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.

I'll try to dig up C|Net's previous foul-ups on Apple rumors.

So far, it hasn't been Cnet the only source. I think I read something similar in sites such as The Register, Zdnet, The Inquirer, and some other sites I don’t remember now.