Apple to use HyperTransport?

Things are starting to blossom from much more reliable news outlets.

I think that this is awesome. If Apple wants to get back in the race they are going to utilize the newest technology as quickly as possible.

P-Worm

I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.

I'll try to dig up C|Net's previous foul-ups on Apple rumors.

hmmm... I think this is in a way a bad thing. only because "it should not be too long" seems like it could mean that there will be a revision between now and when it is used.

Originally posted by rice_web
I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.

I'll try to dig up C|Net's previous foul-ups on Apple rumors.

Click to expand...

You are probably right about cNet screwing up a couple of times, but for me, this is the most reliable source that we have gotten G5 info from. The sources of have gotten much more credible over the last few days. From MacB to MacWhispers to eWeek and now to cNet.

ANice, but don't expect it to be ready at WWDC

This technology is nice. Its an interconnect with room to grow as the 970, 980 blossom.
This tech poses significant relevance to developers, so the WWDC WOULD be the place to discuss this.
So, following my rusty logic, if they discus hypertransport, then they let the cat out of the bag that new Macs are on the way. So it looks like they just may demo new stuff.
But I must still be a hard dose of reality and say that we are looking at early August at best for actually getting one of these in our hot little hands.

Thus the need for smeagol. Many people were so hung up on the new 10.2.7 code named smeagol enabling 64 bit functionalitly. But the 970s from what I understand do 32 bit natively, so no need for rewrites in software.

However, if you are using Hypertransport, and want to enable a new chipset. You need an OS that supports the new chips, and technology, thus the Smeagol. Just my take on it of course, but that makes more sense to me.

Rumor Site Credibility

Hey Arn--

I'm not sure if this would work out, and I don't want to cause any political tension between sites or anything, but it would be really helpful to have something like a "buyers guide" for rumor site reliabilities.

You could go through different rumor sites, their predictions, the reality of those predictions, and then how credible a source that rumor site is. That would be really useful in determining validity of different rumors?

Cheers,
ReeD.

More Hypertansport claims...

Newsfactor also has an article stating that Apple will be using Hypertransport (and an AMD chipset) in the forthcoming Powermas:
"According to preliminary reports -- completely unsubstantiated by Apple -- the G5 will be turbo-charged with IBM's (NYSE: IBM - news) 64-bit PPC 970 processor. The system's 64-bit addressing will be a major step past Apple's current bus architecture. The new machines will also include AMD's (NYSE: AMD - news) Hypertransport technology, which can push data down pipes at speeds in the neighborhood of 12.8 Gigabytes per second. "
For the complete article: http://story.news.yahoo.com/news?tmpl=story&u=/nf/20030612/bs_nf/21715

We'll see soon, I guess....

I'm sooo glad these journalists know more than the gang at arstechnica, who are still trying to get info on exactly what type of bus IBM is using on the 970.

Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.

Or are they just relying on bus speeds rates to say it's HT.

Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.

---

Hannibal should be talking to the IBM PPC 970 architects sometime to get an idea of the SMP topology, and some of the nitty-gritty details answered. When is the question...

Do they really mean gigabytes ? 6.4 to 12.8 gigabytes/sec seems like too much (by, say, a factor of eight).

This might appear to be off-topic, but are we going to be seeing the G5's (970's) soon or is it going to take a while for every mac user's dream to become a reality. How much is this dream machine going to cost, would it be replacing the entire PowerMac line.

Originally posted by ozubahn
Do they really mean gigabytes ? 6.4 to 12.8 gigabytes/sec seems like too much (by, say, a factor of eight).

Click to expand...

It is gigabytes and not bits.
look at their page.

GregGomer, are you sure that the current version of Jaguar would operate OK on a 970? i thought that they had to release an update so that it would work on the 970's... but since they are backward-compatible with 32-bit apps i guess it does make sense that Smeagol would have all the HyperTransport tweaks.

saying that "it should not be too long" sounds like the first batch won't have HT technology... but they'll probably just discuss it at WWDC. this is very sudden news of Apple using HT, sounds like it'll be in the Rev. B 970 machines.

oooohhhhh....

SWEET JESUS!!! I Can't WAIT!!! down with WINTELS!!!!
My Guy at IBM told me the other day that IBM is using AMD alot anyway, and that they are going to be in their workstations and eServers...

Yipeeeeeee!!! bring on the 970s

Apple could use HyperTransport links on the motherboard instead of the PCI bus (and still keep PCI or PCI-X slots behind tunnel chips).

The PowerPC 970 does not host HT controllers that could be used to interconnect the CPUs.
My guess is that all the cache coherency spooping will be done by the chipset and Apple will stay with a dual SMP system.
Unless they have a quad or octo CPU Mac in mind moving from SMP to a more NUMA like architecture would only increase the cost of the whole computer since the PowerPC 970 has no build-in memory controller.

Just to make it clear...

Just so everyone's clear on this, I interpret this to mean that HT will be used to connect the northbridge and the southbridge of the new Power Macs. In the current Power Macs, the northbridge is called U2 and the southbridge is called KeyLargo. To understand this a bit better, check out the current Power Mac G4's block diagram (and the rest of the architecture documentation) at developer.apple.com.

So the weird 970 proprietary bus thing will replace the MaxBus, and HT will partially replace the PCI bus.

HTH
WM

Originally posted by Sun Baked
I'm sooo glad these journalists know more than the gang at arstechnica, who are still trying to get info on exactly what type of bus IBM is using on the 970.

Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.

Or are they just relying on bus speeds rates to say it's HT.

Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.

Click to expand...

To my knowledge the 970 bus is based on the "elastic" POWER4 bus, it just went from 128 bits wide to 32 bits, I don't think IBM is part of the HT consortium.

http://www-3.ibm.com/chips/products/powerpc/newsletter/dec2002/newproductfocus2.html
"The PowerPC 970 implements an Elastic I/O processor interface bus..."

Originally posted by mathiasr
To my knowledge the 970 bus is based on the "elastic" POWER4 bus, it just went from 128 bits wide to 32 bits, I don't think IBM is part of the HT consortium.

Click to expand...

They were on the RIO board, but that doesn't mean anything.

Hannibal should get a lot of the answers on the SMP topology, bus, cache snooping methods, etc. whenever he gets the meeting with the 970 people.

Of course if you have concrete info, spill your guts.

BusinessWeek quotes the same

Originally posted by cb911
GregGomer, are you sure that the current version of Jaguar would operate OK on a 970? i thought that they had to release an update so that it would work on the 970's... but since they are backward-compatible with 32-bit apps i guess it does make sense that Smeagol would have all the HyperTransport tweaks.

Click to expand...

Yah, I'm not in a position to be sure, I'm just speculating from what I've read. But it's my understanding that some upcoming 64 bit chips run 32 bit Apps in a type of emulation, where the IBM chip handles the 32 stuff natively. As to the current Jag working with the 970, probably not, as Arn said, you gotta have some drivers and support in their for the new AMD chipset, Hypertrasnport and the 970. So they'd need the new Jag release to add these few items. But it's my impression that yah, the 970 can run a 32 bit OS and apps just fine.

Now, here's my question, I've seen a few posts saying, dang, we won't see hypertransport till the rev B. I didn't see anything about the HT not being immediately available in the article, so where are we getting that it won't be available with the initial new machines.

Also, is AMD, Apple And nVidia are all on the HT consortium right. So is Hypertransport part of the nForce chipset used with so many AMD motherboards, or is it a completely different and new technology?

Thanks in advance for the info---

rapidIO

As I recall, RIO is one of the proposed PCI replacement technologies. Machines can have both Hypertransport and RapidIO.