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rice_web
Jul 9, 2003, 06:31 PM
Back in the day when the PowerMac had just eclipsed the 1GHz mark, rumors were flying everywhere that an updated G4 core would feature a number of enhancements outside of a megahertz jump. The most significant of these were the support for a higher FSB, an inclusion of double the L2 cache, and double the L3 cache. All of these features would be brought on thanks to the switch to a smaller manufacturing process, allowing these a higher clock rate and larger cache sizes.

The FSB support can only be assumed. Altivec is certainly starved as it is, and even without Altivec, a machine at 1.4GHz should not be on a 166MHz system bus. The rumors of a double-pumped 400MHz system bus are, I'd guess, true.

The L2 cache will almost certainly receive a boost with the extra space available on the chip. It only makes sense that 512K of L2 cache would wind up on the G4. Again, I'd have to believe these rumors are true.

But what about the L3 cache? This is a tough call, because with the extra bandwidth from the higher FSB, the effect of a costly L3 cache is minimal. However, if Motorola were to double the size of the L3 cache, bringing it to 4MB, systems would have the effect of a large L2 cache, a large L3 cache, AND a relatively quick FSB. It'd be a triple whammy.

In fact, if all three improvements were made, and the chip were able to clock to 1.8GHz on the current process, the G4 would easily rival IBM's G5. The G5 would have a similar L2 cache, but would lack an L3 cache. And though the G5 has a tremendously quick FSB, it is definitely a more complicated processor, and pays more heavily on branch prediction failure. In short, it's not as clean as the G4 on some levels. Added to this is the G5's relatively weak Altivec unit, and the G4 is definitely staying for a while.

Lanbrown
Jul 9, 2003, 10:20 PM
The bus will be 200MHz and the cache size can be 4MB, but only 2MB can be used as cache.

http://www.theregister.com/content/39/31424.html’

rice_web
Jul 10, 2003, 12:26 AM
Unless I've seen it elsewhere, I usually consider any news item from The Register a rumor. Is there any press release or from-Motorola information?

Lanbrown
Jul 10, 2003, 08:29 AM
http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=PPCEVAL-SP3-7457&parentCode=null&nodeId=03C1TR04670871b9MM

http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC7457

http://e-www.motorola.com/webapp/sps/site/overview.jsp?nodeId=02VS0llCc5pzMPsvFLn1b23G5nChPn

Even here states that same thing about the cache:
http://e-www.motorola.com/files/32bit/doc/data_sheet/MPC7457EC.pdf

Here is an interesting news release:
http://www.motorola.com/mediacenter/news/detail/0,1958,2322_1901_23,00.html

Another source states third quarter:
http://www.vita.com/npgallery/synergy7457.html

ddtlm
Jul 10, 2003, 10:55 AM
rice_web:

People constantly think that the primary advantage of the L3 is bandwidth, but that's not true. Its advantage is access latency, and even the old 500mhz DDR L3 has far lower access latency than the 1000mhz FSB & DDR-400 system of a G5. Even the most favorable numbers I've seen for the G5 put it's main memory at 3x the latency of the L3, and its probably significantly worse than that.

NNO-Stephen
Jul 10, 2003, 11:56 AM
G4 either needs a quicker FSB (ha) or needs to go.

G5 should be made at 1.0, 1.1, and 1.2Ghz for the PowerBooks, and when G3 gets AltiVec maybe switch to that for the iBooks and the eMac and get a 1.2 and 1.4 G5 in the iMac line.

but again, i'm not running the company and it's not "that simple"

:\

anyway, the G4 has some life left in it, hopefully Motorola won't totally let us down in the final hour of the G4...

rice_web
Jul 10, 2003, 01:31 PM
Originally posted by ddtlm
rice_web:

People constantly think that the primary advantage of the L3 is bandwidth, but that's not true. Its advantage is access latency, and even the old 500mhz DDR L3 has far lower access latency than the 1000mhz FSB & DDR-400 system of a G5. Even the most favorable numbers I've seen for the G5 put it's main memory at 3x the latency of the L3, and its probably significantly worse than that.

Naturally, the distance from the memory versus the distance to the cache favors tremendously the cache. I actually thought I had mentioned this but failed to do so.