An unconfirmed report spelling out some interesting future possibilities about Apple and their PowerPC progress and development:
"Following the microprocessor forum, IBM presented Apple with a handful of PPC 980 alpha samples to begin work on the next generation Powermac due out in 9-12 months. Initial compiler tests showed specfp base 2000 of 1400 and specint of 1200 at 3Ghz. The PPC 980 will have double the L2 cache of the 970, and will still not have an L3 cache option, owing to the fact that the 980 will have a 1x, 2x, 3x, and 4x bus multiplier, which will allow an FSB to run at the chip clock speed if need be, but the plans are to stick to a 2x multiplier, which would mean a 1.5Ghz FSB. The reason why the 980 is appearing only 12 -16 months after the 970 is that Apple chose to engage in parallel development with the Power 5, rather than wait 12-18 months after the fact. The 980 samples that were given to Apple were 90nm chips, as opposed to 130nm chips for the PPC 970 and the Power 5.
For the G5, the next revision is well under way. The bugs on IBM's 90nm process have been squashed, and ramp up will begin within 6 weeks, with intention of having enough chips ready for the next revision G5's due in February. 2.5 - 2.8 Ghz is probably going to be the ceiling of the new revision Powermac G5's based on test yields obtained recently. If everything goes well, 2Ghz may drop out of the equation entirely, and 2.2 Ghz may become the low end, a jump of 500-600 Mhz this revision is realistic, and should be expected. As for the Powerbook G5, only a general timeline is given with a range from April 2004-September 2004 is given, the only obstacle being finding an appropriate cooling technology."
"Following the microprocessor forum, IBM presented Apple with a handful of PPC 980 alpha samples to begin work on the next generation Powermac due out in 9-12 months. Initial compiler tests showed specfp base 2000 of 1400 and specint of 1200 at 3Ghz. The PPC 980 will have double the L2 cache of the 970, and will still not have an L3 cache option, owing to the fact that the 980 will have a 1x, 2x, 3x, and 4x bus multiplier, which will allow an FSB to run at the chip clock speed if need be, but the plans are to stick to a 2x multiplier, which would mean a 1.5Ghz FSB. The reason why the 980 is appearing only 12 -16 months after the 970 is that Apple chose to engage in parallel development with the Power 5, rather than wait 12-18 months after the fact. The 980 samples that were given to Apple were 90nm chips, as opposed to 130nm chips for the PPC 970 and the Power 5.
For the G5, the next revision is well under way. The bugs on IBM's 90nm process have been squashed, and ramp up will begin within 6 weeks, with intention of having enough chips ready for the next revision G5's due in February. 2.5 - 2.8 Ghz is probably going to be the ceiling of the new revision Powermac G5's based on test yields obtained recently. If everything goes well, 2Ghz may drop out of the equation entirely, and 2.2 Ghz may become the low end, a jump of 500-600 Mhz this revision is realistic, and should be expected. As for the Powerbook G5, only a general timeline is given with a range from April 2004-September 2004 is given, the only obstacle being finding an appropriate cooling technology."
