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MacRumors
Feb 9, 2004, 04:29 PM
CNet reports (http://news.com.com/2100-1006_3-5154963.html?tag=nefd_top) that a new version of the Hypertransport specification was released today.

Hypertransport 2.0 is capable of transfering up to 22.4 gigabytes/second while the current incarnation of Hypertransport maxes out at 12.8 gigabytes a second.

Apple has recently adopted Hypertransport for their PowerMac G5 interconnects.

settledown
Feb 9, 2004, 04:31 PM
what does that really mean as far as system speed goes?

jessefoxperry
Feb 9, 2004, 04:31 PM
dear god thats fast

lind0834
Feb 9, 2004, 04:31 PM
New G5s any day?

KEL9000
Feb 9, 2004, 04:34 PM
Originally posted by settledown
what does that really mean as far as system speed goes?

increased data throughput

bobindashadows
Feb 9, 2004, 04:38 PM
Originally posted by jessefoxperry
dear god thats fast

yeah, I'll second that. That's a tad on the speedy side.

Mav451
Feb 9, 2004, 04:39 PM
Hold up. I know the G5's back in August use the same HT technology (i guess spec 1 if this is "2.0") as the Opterons have been using since April.

This probably means that they are definitely prepping for a legitimate launch on the desktop--whether it be a speed bump or revision. A dual 2.2G5 is pretty much automatic and would not be much of a suprise if it was announced anytime soon.

I don't see why they would put this into the existing G5 system because that would lead to an entirely new motherboard...pretty much tossing ou the Rev B argument. New technology usually leads to a new product, not a simple revision...

RBMaraman
Feb 9, 2004, 04:39 PM
Originally posted by lind0834
New G5s any day?

I'm betting we'll see new G5's tomorrow.

Apple was probably just waiting for this announcement because they didn't want to release machines with the technology before the technology was officially announced.

AirUncleP
Feb 9, 2004, 04:41 PM
I'm not sure what this exactly means but I like it.

yoman
Feb 9, 2004, 04:44 PM
Originally posted by AirUncleP
I'm not sure what this exactly means but I like it.

I couldn't agree more.

VectorWarrior
Feb 9, 2004, 04:46 PM
If this is related to new powermacs then surely they would be available immediatly. If there is to be an announcement and then a waiting period why announce this now and not later when the units actually ship.

jholzner
Feb 9, 2004, 04:56 PM
Originally posted by RBMaraman
I'm betting we'll see new G5's tomorrow.

Apple was probably just waiting for this announcement because they didn't want to release machines with the technology before the technology was officially announced.

Well, I don't think we will be seeing this in ANY machines for at least the next six months.

From the article:

Cavalli would not comment on when companies will come out with products, but sources indicate that products could start coming out toward the end of the year

gwangung
Feb 9, 2004, 04:58 PM
Originally posted by VectorWarrior
If this is related to new powermacs then surely they would be available immediatly. If there is to be an announcement and then a waiting period why announce this now and not later when the units actually ship.

What he said....

This is a major enough piece of new technology for there to be significant gaps between announcement and implementation. It's not a trivial bit of technology to implement, so there's going to be a signficant time for testing once they've nailed down the specs.

stoid
Feb 9, 2004, 05:00 PM
The article has a little "products may have this technology by the end of the year disclaimer" at the bottom.

Maybe the 3.0 GHz G5 will sport it though?

If/when the G5 gets shoe-horned into a laptop, will in utilize all the awesome bandwidth features of the G5 desktop? It seems to me that it's the loosening of bottlenecks that really adds to the G5's speed.

The Dreaming
Feb 9, 2004, 05:03 PM
Do you think we'll see a PM update before this technology is implemented? I sure hope this feature is in store for the next G5 revision. Anybody see it happening?

Hemingray
Feb 9, 2004, 05:12 PM
Yeah, I agree, I think it's a bit premature to think that Apple will instantly be coming out with new G5's that use Hypertransport 2.0. I'd love it, but I'm certainly not betting on it.

As to how this all calculates out, does anyone know if the current G5's are even close to max-ing out the current Hypertransport bandwidth? I'm also assuming that, like with FireWire or USB, Hypertransport 1.x can't be upgraded to 2.0.

RBMaraman
Feb 9, 2004, 05:20 PM
Originally posted by jholzner
Well, I don't think we will be seeing this in ANY machines for at least the next six months.

From the article:

Cavalli would not comment on when companies will come out with products, but sources indicate that products could start coming out toward the end of the year

Wait...You thought I was talking about Hypertransport...LOL! Oh my Gosh! I so totally was talking about another technology! LOL! Oh my Gosh! I can't believe you fell for it!

<Silence>

<Silence>

<Crickets Chirp>

Yeah, I'm just trying to keep myself from sounding like a complete idiot. I guess I should really learn to read the articles before I start posting.

rainman::|:|
Feb 9, 2004, 05:23 PM
Originally posted by The Dreaming
Do you think we'll see a PM update before this technology is implemented? I sure hope this feature is in store for the next G5 revision. Anybody see it happening?

completely ignored almost all the posts in this thread, didn't we? ;)

i echo the 3ghz system... but i don't think this will change the G5 form factor. It's not a new technology, just a new/improved standard.

paul

kettle
Feb 9, 2004, 05:24 PM
what would this do for a cluster similar to the Virginia Tech setup?

pilotgi
Feb 9, 2004, 05:27 PM
We won't be seeing any computers with this new technology for a while. It's going to do away with the agp slot.

Know anywhere you can get a graphics card that doesn't use agp or pci?

spinner
Feb 9, 2004, 05:30 PM
looks like another reason to wait for DP 3.0 gHz PM's

floatingspirit
Feb 9, 2004, 05:55 PM
Originally posted by spinner
looks like another reason to wait for DP 3.0 gHz PM's

Oh man! Not another reason for "waiting"!!:eek: :confused:

AVON
Feb 9, 2004, 06:08 PM
How soon are updated G5s coming... I'm wanting to a top of the line in about 2 months...

andyduncan
Feb 9, 2004, 06:10 PM
Originally posted by kettle
what would this do for a cluster similar to the Virginia Tech setup?

Different type of "interconnect." Hypertransport is (primarily?) internal, ie it's for communication between chips on the motherboard of each computer/node, rather than a connection between nodes (such as infiniband). That said, it would make each individual node faster, and therefore increase the speed of the overall cluster.

centauratlas
Feb 9, 2004, 06:28 PM
There are several benefits to this technology, most notably is for MP machines.

Think about this, the more bandwidth going in and out of the processor, the more data you can crunch. For example, getting to main memory is faster etc. (e.g. this isn't just between the CPU and main memory).

But, you say, isn't 12.8 gigabytes/second enough even for a 3GHz processor? For almost every application that would be more than enough even with 64 bit accesses. In all likelihood it would be pretty good for even a dual 3GHz machine, even using vector instructions, for 99% of the desktop applications. However, for dual or more processors, running at >3GHz, it might not.

I would say it would be particularly useful for things like Xserves used in a supercomputer where there is lots of data to be crunched. This would include things like the Virginia Tech machine, rendering farms (e.g. think Pixar) and the like. This is where most of the benefit would go. (It wouldn't help the speed *between* machines in the cluster, but would speed up each individual machine).

The other area it will help is for dual core CPUs when we see them. For example, you might have a two dual core CPUs which would roughly equate to a quad processor. They would need lots of bandwidth.

I'll be interested in seeing these machines whenever they come out - probably 9-12 months, although like everyone, I'd love a G5 PB (or an Apple branded cell phone) with it tomorrow. ;-)

WM.
Feb 9, 2004, 06:28 PM
Originally posted by Hemingray
As to how this all calculates out, does anyone know if the current G5's are even close to max-ing out the current Hypertransport bandwidth? I'm also assuming that, like with FireWire or USB, Hypertransport 1.x can't be upgraded to 2.0.
We can try to do a little back-of-the-napkin math on this. I'll do as much of this as I can off the top of my head. :)

The G5 has two HyperTransport links: a 16-bit one (3.2 GBps max) between U3 and the PCI bridge, and an 8-bit one (1.6 GBps max) between the PCI bridge and K2. The latter is connected to the following, with peak MBps numbers in bold (feel free to challenge/clarify me on the numbers, everybody :) ):

FireWire 100
USB 2.0 ~70 (not a typo; figure one port at 60 MBps and four others at 1.5 MBps each)
Ethernet 125
SATA 2 x 150
Digital audio: 6 channels x 2 ports x 48,000 samples/sec x 24 bits per sample = 1.6 (this is not significant, but I want to cover all the bases)
AirPort Extreme 6.75
ATA/100 100

OK, I don't think I forgot anything. 100 + 70 + 125 + 300 + 10 (rounding) + 100 = 705 MBps. That's about half of the theoretical max.

I chickened out just now and checked the website, and that appears to be correct. I did leave out the boot ROM and the PMU, because I figure their bandwidth is truly insignificant. But I'm not sure about a couple things: my impression is that there's only one FireWire bus for all three ports. Does anyone know if this is correct? Does it really mean that the maximum total bandwidth for FireWire is 800 Mbps = 100 MBps, or is there another 400 Mbps = 50 MBps for the FireWire 400 ports?

Now for the 16-bit link. On the 1.8 and 2.0 GHz configurations, there are three PCI-X slots on two buses. Let's suppose that each bus can run at 133 MHz (which is not supported by the block diagram, but what the heck). 133 MHz x 64 bits x 2 buses = 2.08 GBps. Add this to our 705 MBps number from before and we get 2.767 GBps, which is about 400-some MBps short of the max.

Now, we also have to consider that almost all the I/O bandwidth numbers I've mentioned have been for interfaces that can (theoretically) do them entirely in one direction. But 16-bit HyperTransport is only capable of 3.2 GBps in both directions simultaneously. It can only do 1.6 GBps in each direction. So that may be a design consideration. On the other hand, I have to figure it's pretty rare that every single interface on your system will be sending data to the processor at once (as opposed to being sent data), so HyperTransport would have a big advantage over a unidirectional bus like PCI (?) that would (I think) have a lot of overhead due to switching directions all the time.

It's also somewhat important to note that the number we're actually looking at is not 1.6 GBps, but 1.5625 GBps (someone divided by 1000 instead of 1024), and there's also some overhead due to the address multiplexing and other things that I don't understand much about.

FWIW
WM

For your edification:
http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/art/03107301P1724_01.gif

That's from the developer note.

spencecb
Feb 9, 2004, 06:43 PM
Wow...its always refreshing to see someone on the site that knows what they are talking about....great explenation of everything!

iriejedi
Feb 9, 2004, 06:48 PM
Originally posted by RBMaraman
Wait...You thought I was talking about Hypertransport...LOL! Oh my Gosh! I so totally was talking about another technology! LOL! Oh my Gosh! I can't believe you fell for it!

<Silence>

<Silence>

<Crickets Chirp>

Yeah, I'm just trying to keep myself from sounding like a complete idiot. I guess I should really learn to read the articles before I start posting.

I'm so freaking sad.... I thought you were talking about "HYPERDRIVE" technology!!!
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Pass me the hydrospanner!

"No this one goes there, that one goes there!"-
H.Solo (on hoth)
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-

iriejedi
Feb 9, 2004, 06:49 PM
Originally posted by WM.
We can try to do a little back-of-the-napkin math on this. I'll do as much of this as I can off the top of my head. :)

The G5 has two HyperTransport links: a 16-bit one (3.2 GBps max) between U3 and the PCI bridge, and an 8-bit one (1.6 GBps max) between the PCI bridge and K2. The latter is connected to the following, with peak MBps numbers in bold (feel free to challenge/clarify me on the numbers, everybody :) ):

FireWire 100
USB 2.0 ~70 (not a typo; figure one port at 60 MBps and four others at 1.5 MBps each)
Ethernet 125
SATA 2 x 150
Digital audio: 6 channels x 2 ports x 48,000 samples/sec x 24 bits per sample = 1.6 (this is not significant, but I want to cover all the bases)
AirPort Extreme 6.75
ATA/100 100

OK, I don't think I forgot anything. 100 + 70 + 125 + 300 + 10 (rounding) + 100 = 705 MBps. That's about half of the theoretical max.

I chickened out just now and checked the website, and that appears to be correct. I did leave out the boot ROM and the PMU, because I figure their bandwidth is truly insignificant. But I'm not sure about a couple things: my impression is that there's only one FireWire bus for all three ports. Does anyone know if this is correct? Does it really mean that the maximum total bandwidth for FireWire is 800 Mbps = 100 MBps, or is there another 400 Mbps = 50 MBps for the FireWire 400 ports?

Now for the 16-bit link. On the 1.8 and 2.0 GHz configurations, there are three PCI-X slots on two buses. Let's suppose that each bus can run at 133 MHz (which is not supported by the block diagram, but what the heck). 133 MHz x 64 bits x 2 buses = 2.08 GBps. Add this to our 705 MBps number from before and we get 2.767 GBps, which is about 400-some MBps short of the max.

Now, we also have to consider that almost all the I/O bandwidth numbers I've mentioned have been for interfaces that can (theoretically) do them entirely in one direction. But 16-bit HyperTransport is only capable of 3.2 GBps in both directions simultaneously. It can only do 1.6 GBps in each direction. So that may be a design consideration. On the other hand, I have to figure it's pretty rare that every single interface on your system will be sending data to the processor at once (as opposed to being sent data), so HyperTransport would have a big advantage over a unidirectional bus like PCI (?) that would (I think) have a lot of overhead due to switching directions all the time.

It's also somewhat important to note that the number we're actually looking at is not 1.6 GBps, but 1.5625 GBps (someone divided by 1000 instead of 1024), and there's also some overhead due to the address multiplexing and other things that I don't understand much about.

FWIW
WM

For your edification:
http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/art/03107301P1724_01.gif

That's from the developer note.

Where are they going to fit the "Warp Core"???

WM.
Feb 9, 2004, 06:54 PM
Originally posted by spencecb
Wow...its always refreshing to see someone on the site that knows what they are talking about....great explenation of everything!
I wouldn't say I'm there yet. :) I'd hope that that block diagram is pretty self-explanatory. See how the HyperTransport links and the buses to the processors are the only ones on the diagram represented by two arrows, instead of a solid line? That tells you about bidirectional vs. unidirectional connections (although I wouldn't rely on a detail in a diagram like that to know for sure). The only praise I might allow you to give me ;) would be for doing most of that off the top of my head (I went to the developer site only at the last minute, to confirm everything and attach the image).

It's amazing what you can learn on developer.apple.com, even if you're not a member of the ADC!! :) Check it out!

WM
(not a member of the ADC, although I may be eventually)

Oh, again, if anyone has any corrections/clarifications/challenges on my numbers there, feel free...

WM.
Feb 9, 2004, 06:58 PM
Originally posted by iriejedi
Where are they going to fit the "Warp Core"???
They do have exotic names, huh? "HyperTransport" is sure a long ways from "60x" or even "MaxBus"...that's marketing innovation (ha!) for you.

WM

Rocketman
Feb 9, 2004, 07:14 PM
Originally posted by pilotgi
We won't be seeing any computers with this new technology for a while. It's going to do away with the agp slot.

Know anywhere you can get a graphics card that doesn't use agp or pci?

Wouldn't this help the card vendors from the Siggraph thread (page 1) and be perfect for the on-board quad-980 workstation?

Hypertransport is the inter chip connect bus.

Rocketman

jouster
Feb 9, 2004, 08:18 PM
Originally posted by VectorWarrior
If this is related to new powermacs then surely they would be available immediatly. If there is to be an announcement and then a waiting period why announce this now and not later when the units actually ship.

Because this is not an announcement by Apple.

tortoise
Feb 9, 2004, 08:23 PM
Originally posted by Mav451
I don't see why they would put this into the existing G5 system because that would lead to an entirely new motherboard...pretty much tossing ou the Rev B argument. New technology usually leads to a new product, not a simple revision...


It is a bit more complicated than that as well. The Opteron and the G5 uses the HyperTransport differently in their system architectures. On the G5 it is essentially used as a superfast I/O bus, but otherwise the architecture of the G5 is vanilla SMP and doesn't fully exploit the theoretical capabilities of the HyperTransport technology. There is not a pressing need to upgrade the HyperTransport version primarily because Apple isn't fully exploiting the one they have. Therefore, it would be cheaper for Apple to stick with their current version for at least another year.

The Opteron actually uses the HT as a ccNUMA fabric, not a simple SMP I/O controller. Since HT is basically an AMD owned technology, they exploited it to great effect in their multiprocessor Opteron systems and generally get more out of it. The v2.0 will allow the Opterons to scale well to even larger multi-processor systems than it already does (currently 8-way for Opteron versus 2-way for SMP systems), but I don't see any pressing need on the G5 for even more I/O throughput as there are other rate limiting factors.

Sun Baked
Feb 9, 2004, 08:29 PM
You may see HT2.0 coming quicker than USB2.0 -- about the time DDR2 and PCI-Express show up.

AMD may have made the announcement about supporting a PCI-Express HT Tunnel under HT2.0 -- but as you can see this is mainly helpful for PCI and the bridge to KeyLargo2 and the i/o there (which is basically lashed together with PCI/USB).

HT2.0 won't make the memory, graphics card, or FSB any faster.

Just a bigger bandwidth pipe from the UniNorth 3.x to the PCI bus and i/o.

Stewie
Feb 9, 2004, 08:32 PM
Originally posted by RBMaraman
Wait...You thought I was talking about Hypertransport...LOL! Oh my Gosh! I so totally was talking about another technology! LOL! Oh my Gosh! I can't believe you fell for it!

<Silence>

<Silence>

<Crickets Chirp>

Yeah, I'm just trying to keep myself from sounding like a complete idiot. I guess I should really learn to read the articles before I start posting.

LOL! A very good recovery

benpatient
Feb 9, 2004, 08:53 PM
not to mention you guys forgot to include the RAM bandwidth...

even with that, though, 2 processors aren't using HT1.0 fully, anyway...

gregorypierce
Feb 9, 2004, 08:54 PM
Why this is cool, we need hyperthreading in the cores like yesterday.

gregorypierce
Feb 9, 2004, 09:01 PM
Originally posted by iriejedi
Where are they going to fit the "Warp Core"???

Bah - there's plenty of space between the PCI slot and the modem port. :D

Catfish_Man
Feb 9, 2004, 09:02 PM
Originally posted by benpatient
not to mention you guys forgot to include the RAM bandwidth...

even with that, though, 2 processors aren't using HT1.0 fully, anyway...

Since the ram doesn't go over HT, no, they didn't forget.

The main thing that's cool about this is that it bridges to PCI-Express easily, which should keep Apple from getting left behind by Intel and Co. when they switch away from AGP. Maybe let them simplify that block diagram a bit too.

kansast
Feb 9, 2004, 09:31 PM
Isn't Apple connected some kind of way with some "hypertransport" consortium ? or something like that ?

Just wondering if that is the case, might they not have been aware of this change coming for awhile ? and if so, maybe it is possible to see it hopefully sooner than later in future G5 releases ?

Still holding on to my G4/450.. one of these days gonna get that new Mac.. and they just keep gettin' faster and faster :-)

WM.
Feb 9, 2004, 09:36 PM
Originally posted by Sun Baked
...KeyLargo2 and the i/o there (which is basically lashed together with PCI/USB).
Eh? Certainly the external USB ports and the AirPort card are on a PCI bus, but I wouldn't say the SATA, FireWire, or Ethernet ports on K2 have much to do with USB or PCI.

On the other hand, there certainly could be something you know that I don't. As I said, I'm not a member of the ADC, and my understanding is that there were sessions at WWDC about the G5's architecture, which I certainly don't have access to. And I suppose anyone who does is probably under NDA...
HT2.0 won't make the memory, graphics card, or FSB any faster.

Just a bigger bandwidth pipe from the UniNorth 3.x to the PCI bus and i/o.
Agreed.

WM

Supa_Fly
Feb 9, 2004, 09:51 PM
Just reading while listening to Swordfish soundtrack and was wondering.

VT's Supercomputer needed low-latency interconnects and opted to use Infineon fibre connection and not the SPDF that Apple offers; why?? Bandwidth for computational power??

Now apply this new HyperTransport ver2.0 for this in Dual or Quad G5's in a Rack mount....say XServe Supreme and link to XRaids.

Or better yet implement DDR-II memory with said above and allow HyperTransport as an effective data bus Throughout the mobo......to everything.

Say 12x SuperDrives, all 3 nah say 4 FULL PCI-X 133Mhz 64-bit slots or maybe PCI-Extreme. Now what about PowerMac G5s or Xserves able to use memory with supremely low latency across an entire network (local, but imagine over 3x the speed of T1 internet connection networks). Your G5 doing gene splicing, applying nanotechnology in a hypothetical realm to build synthetic materials or even bones, ligaments, tendons, that are built from existing molecules in nature yet modified to 100x tensile strength of Titanium......but to research this from scratch all the systems need low latency from memory to cpu's to HDD to input output (including Infineon Fibre connection and local 10000Base T Ethernet etc).

Well you get my drift, the Enterprise computer with a sweet voice, sweet mind, and can go 0-naked in a heartbeat.

LOL:D

Seriously we might have to wait to see what AMD can do with this first before hoping for it in Apple products ....only because they've used it first thus may have more expertise.

invaLPsion
Feb 9, 2004, 10:04 PM
According to NeatGekko we could see new powermacs at anytime in February and definitely in February. He suggests any Tuesday as a possible release date and is hoping for tomorrow. He did not comment on the powermacs using this new technology, however.

Rincewind42
Feb 9, 2004, 10:09 PM
Originally posted by kansast
Isn't Apple connected some kind of way with some "hypertransport" consortium ? or something like that ?

Just wondering if that is the case, might they not have been aware of this change coming for awhile ? and if so, maybe it is possible to see it hopefully sooner than later in future G5 releases ?

Yes, Apple is a member of the HyperTransport Consortium.

Rincewind42
Feb 9, 2004, 10:13 PM
Originally posted by Prom1
VT's Supercomputer needed low-latency interconnects and opted to use Infineon fibre connection and not the SPDF that Apple offers; why?? Bandwidth for computational power??

S/PDIF is an audio connect - toslink :). They won't be getting very much bandwidth off of that!

However, they do use the built in gigabit ethernet as a backup, but ethernet isn't as low latency.

Frohickey
Feb 9, 2004, 10:14 PM
G5s do not use HyperTransport to talk between CPUs to main memory. HyperTransport is only used to talk between the north bridge to the south bridge (8 bit at 400MHz), and between north bridge and PCI bridge (16 bit at 800MHz).

WM, you cannot add the PCI budget to the rest of the I/O budget. Since the busses are separate, the budgets are separate. So, in effect, there is ample headroom on both busses (approx 705 and 800[x2], on the 8 bit at 400MHz), (2.08 and 1.6[x2], on the 16 bit at 800MHz).

What is going on here is in AMD's best interest since they use HyperTransport as their processor interconnect. They need to get that up to higher transfer rates or else their fast processors will go hungry for data. Current Opterons use three 16 bit at 1600MHz HyperTransport busses, thats 9.6GBps each way!

Frohickey
Feb 9, 2004, 10:16 PM
Originally posted by Prom1
Well you get my drift, the Enterprise computer with a sweet voice, sweet mind, and can go 0-naked in a heartbeat.

LOL:D


First dibs on the Holodeck!!! :D

Rincewind42
Feb 9, 2004, 10:34 PM
Originally posted by Frohickey
WM, you cannot add the PCI budget to the rest of the I/O budget. Since the busses are separate, the budgets are separate. So, in effect, there is ample headroom on both busses (approx 705 and 800[x2], on the 8 bit at 400MHz), (2.08 and 1.6[x2], on the 16 bit at 800MHz).

Actually, his original analysis was right. The south bridge has to go through the PCI bridge to get to the north bridge, which means that there is 3.2 GBps bandwidth to everything but RAM & AGP, and 1.6 GBps max beyond PCI-X.

WM.
Feb 9, 2004, 10:52 PM
Originally posted by Rincewind42
S/PDIF is an audio connect - toslink :). They won't be getting very much bandwidth off of that!

However, they do use the built in gigabit ethernet as a backup, but ethernet isn't as low latency.
I think it was a joke...notice the Swordfish reference. I've only seen a bit of that movie, but I have the impression that there's a lot of meaningless technobabble tossed about. :)

Admittedly, my techno-nerd shields were up too and I was ready to come out with debunking guns blazing, but then I re-read it...

:cool:

WM

sethypoo
Feb 9, 2004, 10:53 PM
Originally posted by AirUncleP
I'm not sure what this exactly means but I like it.

Hear hear, sounds fast.

:p :D

huckleup
Feb 9, 2004, 11:06 PM
Originally posted by Rincewind42
S/PDIF is an audio connect - toslink :). They won't be getting very much bandwidth off of that!


Just a techie point - S/PDIF (Sony/Philips Digital Interface) is not the same thing as Toslink. S/PDIF is an audio transport protocol, whereas Toslink is a physical connector used with optical fiber. Toslink connectors can be used for connecting anything - S/PDIF just happens to be one of those things. Toslink is also used on e.g. 8-channel audio I/O in ADAT systems. S/PDIF is also quite often sent over copper wire and connected via RCA connectors.

Anyway, back to HT:

Wow, if only hard drives could keep up with that! Imagine sending an entire 20GB worth of hard drive data over a wire in 1 second! That would be my entire MP3 collection...

Frohickey
Feb 9, 2004, 11:14 PM
Originally posted by Rincewind42
Actually, his original analysis was right. The south bridge has to go through the PCI bridge to get to the north bridge, which means that there is 3.2 GBps bandwidth to everything but RAM & AGP, and 1.6 GBps max beyond PCI-X.

Erp. My fault. You are right. I was thinking of something else.

Ensoniq
Feb 9, 2004, 11:17 PM
Just a quick note...

I am NOT AT ALL predicting Apple will be supporting HyperTransport 2.0 in their upcoming G5 machines. (Whether they be released tomorrow or in months from now...)

BUT ... remember that Apple is a member of the HyperTransport Consortium. And although Apple makes it a habit to not comment on unannounced products, you can bet your butt that Steve Jobs and AMD have a very clear arrangement where Jobs and Apple knew about HT 2.0 long before the announcement today.

I have no doubt that Apple has been working on HT 2.0 machines in their labs for as long as AMD had a working spec for it. Today's announcement is no surprise to Apple, and does not mean there's "lots of work to do" which could prevent Apple from using it for a long time.

Apple will use it as soon as possible...sooner rather than later. Because to use HT 2.0 before any other company will be one more check Apple can add to their list of firsts. Jobs loves doing things like that. So don't be surprised to see HT 2.0 appearing in the G5 right alongside the 3.0+ GHz G5s when they are available. (Again...not saying WHEN it will happen, just that you can be sure it will.)

wizard
Feb 9, 2004, 11:58 PM
Good questions. ATI indicated years ago that they would support HyperTransport, but we haven't seen anything from them. Nvidia apparently has a chip that supports hypertransport that works in conjunction with a northbridge. Not sure how it well it works or if it can work with out Nvidia's north bridge.

It does make one wonder what Apple will implement in the future. On a laptop this owuld be ideal because you would get rid of an agp port.

You are right it will be awhile before we see this. I do hope that it gets adopted as a video chip interface but I don't believe that that is written in stone.

Thanks
Dave



Originally posted by pilotgi
We won't be seeing any computers with this new technology for a while. It's going to do away with the agp slot.

Know anywhere you can get a graphics card that doesn't use agp or pci?

kettle
Feb 10, 2004, 03:00 AM
So if this technology is good for processors, more so multi processors, could this be a stepping stone for a dual core G5 in a laptop?

Mav451
Feb 10, 2004, 03:34 AM
heh no quite yet. Considering the problems of even putting a single G5 into a laptop at this point, two would be out of question--toasty lap i would say :(

Considering many of the low power Opterons can run @ full speed using only 30 watts, with the 970FX and its successors, i don't see this being at all difficult later on. The later on part will be quite a bit later unfortunately, but again, 2 cpus in any laptop hasn't been done yet (correct me if i'm wrong).

Lanbrown
Feb 10, 2004, 07:43 AM
Originally posted by jholzner
Well, I don't think we will be seeing this in ANY machines for at least the next six months.

From the article:

Cavalli would not comment on when companies will come out with products, but sources indicate that products could start coming out toward the end of the year

I agree. When a spec/standard is released, that means that all parties are happy with where it's at. Once products are made and a flaw is found, that may not be correctable. So trying to jump the gun and get products out as soon as its released is asking for problems. What would happen if a last minute change was made one week prior and a company produced one million chipsets. That is potentially a big waste. Some companies will gamble and release products that follow the interim release, but they usually say there is no guarantee that it will be compliant. Some 100Mb gear and later gigabit gear was like that. I implemented both of those in an enterprise environment before they were officially released. 10-gigibit gear is another example, Cisco was selling gear before the standards body released it. They did say it would be compatible with the official spec when available though.

When there is a pressing need, companies will typically release products that meet the proposed spec.

Lanbrown
Feb 10, 2004, 08:03 AM
Originally posted by Ensoniq
Just a quick note...

I am NOT AT ALL predicting Apple will be supporting HyperTransport 2.0 in their upcoming G5 machines. (Whether they be released tomorrow or in months from now...)

BUT ... remember that Apple is a member of the HyperTransport Consortium. And although Apple makes it a habit to not comment on unannounced products, you can bet your butt that Steve Jobs and AMD have a very clear arrangement where Jobs and Apple knew about HT 2.0 long before the announcement today.

I have no doubt that Apple has been working on HT 2.0 machines in their labs for as long as AMD had a working spec for it. Today's announcement is no surprise to Apple, and does not mean there's "lots of work to do" which could prevent Apple from using it for a long time.

Apple will use it as soon as possible...sooner rather than later. Because to use HT 2.0 before any other company will be one more check Apple can add to their list of firsts. Jobs loves doing things like that. So don't be surprised to see HT 2.0 appearing in the G5 right alongside the 3.0+ GHz G5s when they are available. (Again...not saying WHEN it will happen, just that you can be sure it will.)

All members of the consortium had access to it, not just AMD or Apple. The whole point of a standards/spec body is to get everyone's input. If one company did all of the work, no one would want to use it. Some members may have more influence then the others though. Want to know who knew about HT 2.0 before it was announced; go here:
http://www.hypertransport.org/org_members.html

Rincewind42
Feb 10, 2004, 09:09 AM
Originally posted by kettle
So if this technology is good for processors, more so multi processors, could this be a stepping stone for a dual core G5 in a laptop?

A dual core CPU is quite a different beast from two connected CPUs. They tend to use a rather custom connection fabric that runs at CPU speed and basically allows them to share a single often large cache. So HyperTransport, while nice, is not really a consideration here.

Rincewind42
Feb 10, 2004, 09:10 AM
Originally posted by WM.
I think it was a joke...notice the Swordfish reference.

Admittedly, my techno-nerd shields were up too and I was ready to come out with debunking guns blazing, but then I re-read it...

Heh - you had the advantage(?) of having seen any of Swordfish and possibly of more sleep to go on too at the time :D . I just kinda ignored the rest of the post because it seemed incoherent to me...

ClimbingTheLog
Feb 10, 2004, 10:48 PM
This won't show up in a G5 machine, it'll be in the 980 G6 version, this summer/shipping in September.

Opteron
Feb 11, 2004, 02:42 AM
Apple doesn't really use hyper transport, in the fullest of the sence, since both processors still communicate to each other and the System RAM through a north bridge.

The AMD 64 chips (and other lessr know ones) have this function on-chip, thus giving it true 'Hypertransport.' See the AMD site for a technical white paper on the tech.

Supa_Fly
Feb 11, 2004, 06:30 AM
Frohickey

First dibs on the Holodeck!!! Man I'm always getting seconds.;)

WM

I think it was a joke...notice the Swordfish reference. Actually I was serious, LOL. But still was wrong.

huckleup

Just a techie point - S/PDIF (Sony/Philips Digital Interface) is not the same thing as Toslink. S/PDIF is an audio transport protocol, whereas Toslink is a physical connector used with optical fiber. Are you sure S/PDIF isn't on optical fibre? I had a Sony Mini-Deck that supported S/PDIF in the form of Optical Cable for my Mini-Disc recorder/player, and I did see that beautifully bright red light shine through when the cable was bent.

HT and PCI bus' can be used to carry the same kinds of data throughout the mobo, right? I mean why not? Sure I know they don't necessarily compete.

HyperTransport is HyperTransport whether you choose to connect cpus to memory or not, right? nVidia has a video card based on its technology doubt its the same kind of usuage that AMD uses (GPU to memory without a controller of some sort.)

Good to see IBM is a member as well.

Do I really come off as being scatter brained, often?? trouble with being a Gemini is being missunderstood.

huckleup
Feb 11, 2004, 01:00 PM
Originally posted by Prom1

huckleup

Are you sure S/PDIF isn't on optical fibre? I had a Sony Mini-Deck that supported S/PDIF in the form of Optical Cable for my Mini-Disc recorder/player, and I did see that beautifully bright red light shine through when the cable was bent.


I never said that S/PDIF isn't available over optical fibre using Toslink connectors. It most definitely is, but it is also available over copper wire using RCA connectors. I was clarifying the difference between a physical connector and a protocol. Just like the fact that Ethernet can be transported over various physical layers, like coax and BNC connectors (old world), twisted pairs and RJ-45 connectors (10xBaseT) or even Air (802.11x). S/PDIF is just a protocol and is independent of whatever physical layer is used. Toslink is just a physical connector, just like BNC, RJ-45 and RCA are physical connectors. Toslink connectors are also used for things other than S/PDIF, the example I gave was ADAT optical I/O (there may be other places that Toslink is used, but I don't know).

leftbanke7
Feb 11, 2004, 02:03 PM
Originally posted by centauratlas
I'd love a G5 PB (or an Apple branded cell phone) with it tomorrow. ;-)

With my luck it would be compatible with every phone company except Verizon

Supa_Fly
Feb 11, 2004, 03:04 PM
Thanks for the clarification Huckleup. I didn't realize what you meant until now. Wish that I could be clear when explaining things.;)

WM.
Feb 11, 2004, 05:57 PM
Originally posted by Prom1
WM

Actually I was serious, LOL. But still was wrong.
Whoops. *blush* (Why isn't there an emoticon for that?) I guess I was trying to give you the benefit of the doubt. :)
Do I really come off as being scatter brained, often?? trouble with being a Gemini is being missunderstood.
Yay, Gemini power!!! :D

WM (yes, I really am one)

brooklyn
Feb 11, 2004, 07:09 PM
Originally posted by AirUncleP
I'm not sure what this exactly means but I like it.

It means that this baby has a FLUX CAPACITOR and will enable you to time travel at 2.5 Gigs!

Wait a minute, Doc. Ah... Are you telling me you built a time machine... out of a PowerMac G5?

Can't wait!