I'm not sure what to think about this G5 thing...

[marsmacguru]

Deep within the realm of the IBM PowerPC web-page, I found a few interesting things.... 1: The G5 is currently in production (building up volume)
2: We're talking some serious speed, here.
3: We might be waiting a little longer than expected, but the new products will exceed our expectations.

My professional opinion.... If you have a G3, you may as well wait. If you have a G4, wait. If you have anything that doesn't start with a "G", Buy a quicksilver. They make your 603's and 604's look like ancient relics, and the speed differences will blow you away. After this new breed emerges, we'll all wait for 100GHz G12's before buying again. And that might also be sooner than we think.... Intel buyers beware. Your products will be more outdated than ever.

[Ensign Paris]

and the address is...

[Kela]

www.copypaste.com

[Ossa]

Flame me if I'm being a little dumb here but arent we waiting for G5 stock from Motorola not IBM? I know they both make mac processors but IBM aren't utilising altivec, right? So these G5's are gonna be different....
Please paste the url :)

[Ensign Paris]

I don't think the G5 will have Altivec

[Ossa]

Originally posted by Ensign Paris
I don't think the G5 will have Altivec

You are joking right? Surely were not gonna be taking a step back and losing vector parallel processing? I thought it was motorolas baby - with some more mileage left to go for quite a while?

Questions, questions.... :)

[eyelikeart]

as much as I don't typically like talking about this stuff...

I've read in a couple places where the G5 processor supposedly won't use Alti-Vec like the G4....but who knows...

I'm just waiting patient for some solid evidence.... :p

[mischief]

I think Apple will switch to rats from hamsters and finally discontinue it's line of gerbils in the iBook. The switch to chinchillas will take more time and the fabled weasels are still in R&D.

Meanwhile AMD has announced better lifespan on their cocaine-addicted mice and Intel has announced all new methamphetamine drips for it's gerbils.

[Catfish_Man]

Every rumor I've ever heard has had Motorola producing the G5. Also, a lot of the rumors were saying that they were working on improving Altivec performance. These rumors appeared to be fairly accurate (although I could be wrong about that).

[Durandal7]

I found this about the 750fx, maybe this will be going in iBooks in the future.
750FX-1GHZ (http://www-3.ibm.com/chips/products/powerpc/newsletter/oct2001/new-prod1.html)

[Ossa]

From what I have seen on most boards and rumor sites Altivec is up to version 2 and operating at 256 bit in the G5 I suppose this sounds quite feasible. Yay! Bring it on

I like eyelikearts attitude "I'm just waiting patient for some solid evidence...." I wish I could be patient but its difficult for me when the Apple product lines in limbo. I feel like a kid at Christmas wanting to open his presents early :p

[voctronic]

I think I found it:

http://www.research.ibm.com/journal/rd/435/check.html


and I don't think they're talking about the Mac G4 or G5, but rather their own designations for their processors.

[PyroTurtle]

that site is the original plans and ideas for what we now know of as the G3...originally (if i remember right) it was to be called G5 because of the 604 numbering and instead of calling it a 605 it was to be called a G5...instead it was the 3rd generation of apple processors...pre-powerPC, powerPC, G3....
if you'll look, the article goes back to 1994 info....

[Xeri]

Not missing the fact that that page is information about IBM's S/390 processors? Read it. It is a CISC-based architecture used in certain IBM product lines. It is in no way related to the POWER or PowerPC families of RISC processors.

Read the *@&#^%! article, please.

[Xeri]

I also might add that I'd find it very hard to believe Apple would buy into a new high-end processor that does not support Altivec, considering all the effort they have put into optimizing various parts of Mac OS X for it.

The performance would have to be so overwhelming increased so as to be able to emulate Altivec at a decent pace (which, ironically, would still make Altivec a decellerator to vectorized code since it would then be emulated.)

[spikey]

To have an imac with altivec and a powermac without, is stupid.

[eyelikeart]

I agree....which is why I'm saying I'm not positive but I thought I remember seeing something about them some months ago....

I could be wrong...

personally I don't think we'll see them without Alti-Vec either....it would be a complete waste....

[Unregistered]

you do realise the page is about the IBM S/390® Parallel Enterprise Server™—Generation 5 and Generation 6, right!
http://www-1.ibm.com/servers/s390/pes/

[AndreHAL]

Motorola MPC8540
Features:

e500 "Book E" Processor 600MHz - 1GHz
256KByte On-chip L2
128Gb/s On-chip Fabric
333MHz DDR Memory Controller
Advanced I/O Ports

RapidIO
64b PCI-X
dual 10/100/Gbit Ethernet
General Purpose parallel I/O port

4-Channel DMA
Interrupt Controller (8 discreet or 16 serial)
DUART Serial Interface
Modular Design

I've heard the G5 is supposed to be a book e processor.....speculate for yourselves

http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655

[KingArthur]

I understand everyone's conern about the lack of an AltiVec 128-bit subprocessor, but you have to realise, if the G5 is a true 64-bit processor, then we are talking twice the data in one cycle for everything BUT vector processing (which would be halved). Other than graphics design, vectors are not used a WHOLE lot. Even in graphics, probably at least a quarter of cycles are not vectors. Now, if we see a say...1.2Ghz 64-bit processor with ddr ram, 512k on chip L2 cache @ 1.2Ghz, and a 200Mhz system bus, you are probably about just as fast when rendering your graphics as with a G4 and about 3x as fast in most other activities. You do realize that with G3s and G4s running at the same frequency, the G3 is actually faster (the G4's only edge is vector-processing). Let us think further, now. Mac OS 10.1 can support up to 32 procecssors simultaniously. What about when Apple puts two of these 64-bit processors in the machine, or even more? The current G4 design can only work with up to 2 processors. If IBM makes these chips with support for up to say 4-8, what then for a powerhouse system.
Rumors also say that IBM has been working on its own vector processing engine. Who knows: IBM may blow our minds away with a massive processor, soon.

Well, enough rambling for me.
http://www-3.ibm.com/chips/products/powerpc/newsletter/oct2001/new-prod1.html

[mischief]

Ooooooooh........major Geekgasm. That's TASTEY!!!High speed bus capability and variable chip speed, hooboy.:p :cool:

[eyelikeart]

glad to see I'm not the only one who knows about this... :p

[jaykk]

Accoring to CanadaComputes.com its a safe bet..

http://www.canadacomputes.com/v3/story/1,1017,7912,00.html?tag=81&sb=124

[mischief]

When.

If Apple implements this in March, there'd be a possible:
200Mhz bussed
4GHZ
true 64 bit, splittable-within-chip cached

4 processor
DDR
2Gb system RAM'd
dual native fibre SCSI
G5!!!!!!!!

(okay so I'm guessing about SCSI)

Damn, that'd make Wintel heads take notice. I'll call mine Glamdring thank you.Now if I could just get Narsil outa Woz, I'll be happy.

[mozez]

i don't think apple will implement scsi again, and with great reason, one, they already dropped scsi becuase of price, as well as the fact that now ata 133 comes close and can take 10,000 rpm drives for only a third the cost. there are rumors about ultra scsi 320 but the cost of those will be huge. scsi has laid dorment for a few years, it is due for a comeback. why would apple drop altivec, well, one, ibm has full rights to that engine and they choose not to use it, there is a reason why. speed difficults in higher amounts bog it down, and the only way it is good is if you optimize to use it. photoshop has optimized for it and it's awesome, dvd ripping, aw yea, and others. but many don't, which makes it useless, and like it was said above, if you can double the chip speed and make it true 64 bit, it's gonna dominate, thus, cost is dropped, speed is increased as well as the main thing here people, sales and profit, that's what it's about. you might not like it, but apple knows it. so...

[KingArthur]

Originally posted by eyelikeart
glad to see I'm not the only one who knows about this... :p

The problem is that many Mac users think like PC users, just slightly differently. PC users see 2Ghz! and take that for face value not realizing that the 20some stage pipeline of the P4 is narrow and inefficient and the 64 or 128MB of PC100 RAM slows them up. The Mac users see Alti-Vec! and take that for face value not realizing that speed does matter and the lack of DDR RAM and system bus speed keeps Macs slower than they could be. Both sides are TRAINED by Intel and Apple to think in these ways. We need to think past Alti-Vec, looking at the whole picture, and be better than those PC users.



-------------------------------------------Your Sovergn King-------------

[kansaigaijin]

[.instead it was the 3rd generation of apple processors...pre-powerPC, powerPC, G3....
if you'll look, the article goes back to 1994 info.... [/B][/QUOTE]


ppc 601, ppc 604, G3, G4 . . .

[Unregistered]

[QUOTE]Originally posted by KingArthur
I understand everyone's conern about the lack of an AltiVec 128-bit subprocessor, but you have to realise, if the G5 is a true 64-bit processor, then we are talking twice the data in one cycle for everything BUT vector processing (which would be halved).

Um, that's not how it works. It is true that a 64-bit processor can handle 64-bit word, which is obviously twice as long as a 32-bit word. However, each integer unit can still only process one word at a time. The only difference is that the words are larger, so you can have extra precision, which most people don't need (in fact, the main advantage of a 64-bit processor is that 64-bit addressing allows you to have much more memory than a 32-bit chip, which IIRC is limited to 4 GB). It does not mean that the words are processed any faster. Let me repeat that again: there is no inherent reason why a 64-bit chip should be much faster than a 32-bit chip (you can't just merge two 32-bit words into one 64-bit word and pretend that's like processing them separately...that's like saying that you can solve the two expressions (1 + 4) and (2 + 7) by solving the single expression (12 + 47)...it doesn't work that way!). The 64-bit chip is just able to access a lot more memory.

Altivec, in contrast, is a 128-bit wide vector unit. The key difference with Altivec is that it doesn't process a single 128-bit wide word. Instead, it processes either four 32-bit words, eight 16-bit words, or sixteen 8-bit words. This is why Apple can claim it is "up to 16 times faster" for some instructions. Specifically, if you're doing the same instruction to a bunch of 8-bit words (and it must be the same instruction - that's why it's called "Single Instruction, Multiple Data"), then it will take you at least 16 cycles on the 32-bit integer unit (note that we'll only be using 8-bits of each 32-bit word - the rest will essentially just be unused space). In contrast, Altivec could take the sixteen 8-bit words and process all of them in one cycle: hence it can be up to 16 times faster. Note that with a 64-bit processor, it would still take 16 cycles - not any faster than the 32-bit processor (the only difference is that we'd have 56 bits of unused space for each word that was processed rather than 24 bits of unused space).

Perhaps a concrete example would help. Say that you have eight numbers: 500, 501, 502, 503, 504, 505, 506, and 507. Say that you decided to use a 16-bit word to store each of these numbers. Now assume that the operation you wanted to perform was to add 1 to each of these numbers. With a 32-bit chip, this would be eight separate operations: first you'd compute 1 + 500, then 1 + 501, then 1 + 502, and so on until 1 + 507. The 64-bit chip would do the same thing - the fact that you can handle 64-bit words (which are unnecessary for this problem) doesn't help you at all (what are you going to do, try to merge the first two operations by computing 1 + 500501 or something?). But Altivec does help you, because in a single operation it can just take the vector [500 501 502 503 504 505 506 507] and add one to each element, spitting out [501 502 503 504 505 506 507]. That's exactly the output that you wanted, and it only took a single operation!

Now, where the 64-bit chip would help you is if you were working with really, really, really big numbers. Say you had the number 2^42 and you wanted to add 1 to it. You wouldn't necessarily be able to represent 2^42 with a single 32-bit word, so the 32-bit integer unit obviously would not be able to carry out that operation in a single cycle. But the 64-bit processor would have no problems with such a large number, because it can handle 64-bit words (also note that Altivec probably would have problems, since I believe the largest word it takes is 32-bits...it's just that it takes up to four of them at a time). However, most personal computer users have no need for such large numbers, so a 64-bit processor really doesn't help them very much (and at any rate, all of the floating point units already handle 64-bit "double precision" floats).

As for all of the people who think the G5 is just around the corner, I wouldn't hold your breath. I don't have any inside information, but a little common sense seems in order. Remember, most of the G5 rumors came from a single source, quoted repeatedly on both The Register and Mac OS Rumors. But that source clearly lacks credibility, since among other things he/she claimed that the G5 would definitely debut at MWSF (which it did not, unless I really missed something in the Keynote). Furthermore, do you really think it's likely that the G5 would be released *before* the Apollo G4?? I think there's a good chance we will see the G5 before the year is it, but I would be really surprised if it happened anytime in the next few months. Hopefully we will see the Apollo G4 very soon however. It's clear that they need to bolster the G4 Pros vis a vis the G4 iMac - the only question is will the Apollo be as fast as rumored (up to 1.4 Ghz). If it is that fast, I certainly wouldn't advise people to wait around for the G5, which probably wouldn't be released until at least the Fall, and at any rate will have unknown capabilities (remember, the only performance data we have on it came from the now-discredited Register source).

[Buggy]

That was one of the best explainations I have read regarding how 32 bit, 64bit and altevic workd.

THANKS!!!


- to bad you do not have a name. :)

[Unregistered]

"now. Mac OS 10.1 can support up to 32 procecssors simultaniously."

Mac OS X 10.1 can only handle 2 processors..

future version might be able to handle more but 10.1 can only work with two.

[rastalin94]

Is Altivec just Apple's versoin of SIMD as in SSE for Intel and 3-D Now from AMD?

[jaykk]

According to As the AppleTurns, G5 is out already in germany -
http://www.appleturns.com/

[beigemac]

I don't care what comes out or what mhz systembus or or processing bits it has! I just want something that renders 3d faster than a PC user using AMD's. You know its ***** being a mac user who use 3d applications on a professional basis! with the launch of Maya and os X i thought finally mac is in the 3d game! Don't get me wrong OSX rocks for 3df in theory but its the sagging hardware that is running the OS in terms of 3d performance. Anyway is'nt jobs CEO of Pixar. So when in the hell are we gonna c pixar renderman on the Mac platform rather than just PC and SGI!

[ipiloot]

Well, as I noted, some people mix elegantly vector graphics and vector computing.
They are very different things (althrough vector graphics can ask for vector computing, but so can do Photoshop or Quictime), which are not directly related.

[Unregistered]

Originally posted by rastalin94
Is Altivec just Apple's versoin of SIMD as in SSE for Intel and 3-D Now from AMD?

In the sense that both have the goal of performing a single instruction on multiple pieces of data, yes, but keep in mind that there's unanimous agreement that Altivec is far superior to any Intel or AMD implimentation. In MMX, SSE, 3DNOW, etc. you don't actually have a separate dedicated vector processing unit, so it's not nearly as fast as Altivec. I assume that this is simply because there isn't enough room on the die for extra stuff like the vector unit (the Pentiums and Athlons already have too many transistors as it is), although perhaps it could be related to the instruction set architecture somehow (but I can't really see why that would be true). I've also heard that Altivec is substantially nicer to program for than MMX etc.

To Buggy: glad the explanation was useful.

Mike

[Unregistered]

Originally posted by rastalin94
Is Altivec just Apple's versoin of SIMD as in SSE for Intel and 3-D Now from AMD?

In the sense that both have the goal of performing a single instruction on multiple pieces of data, yes, but keep in mind that there's unanimous agreement that Altivec is far superior to any Intel or AMD implimentation. In MMX, SSE, 3DNOW, etc. you don't actually have a separate dedicated vector processing unit, so it's not nearly as fast as Altivec. I assume that this is simply because there isn't enough room on the die for extra stuff like the vector unit (the Pentiums and Athlons already have too many transistors as it is), although perhaps it could be related to the instruction set architecture somehow (but I can't really see why that would be true). I've also heard that Altivec is substantially nicer to program for than MMX etc.

To Buggy: glad the explanation was useful.

Mike

[KingArthur]

Thanks for clearing up the usefulness of 64-bit processors and their disadvantages. I have had to make MANY of my own interpretations about how processing occurs since few on this board actually know what they are talking about. I do have a question, though: OS X can automatically utilize the vector processing on certin operations that it recognizes right? So wouldn't it be logical that Apple would build in an emulator in OSX so that 64-bit processing may be utilized more? I do realize that a many applications would have to be rewritten to utilize 64-bit processing fully, but is there not something that could be done to the OS also?


To the Person who said that OS X can only handle 2 processors:
I have read reports that it is not OS X that is limiting the number of processors in the system (I am almost certin that it can handle up to 32 simultanious processors). It is the archetecture of Motorola's G4e's that only allows duel processors. This is what I have gathered form various soruces.


Just for anyone who may like to learn somewhat how processors work...check out arstechnica.com .

Although I do not always completely know if the info that I provide is accurate depictions about how processors and hardware in general work, I do grasp new concepts easily. Sorry if I confuse anyone, but unless I make my own assumptions after gathering info, there would be HUGE gaps in some of my responses (which for the most part are fairly on target).

Also, I too do not believe we will see the G5 until MW July or later. It would not be a logical move for Apple to release it this early unless of course Apple was developing Apollo for the iMacs, which I think would be a big mistake on their part.

[DarkNovaMatter]

OSX can support up to 32 processors, the only problem is only most programs are only written to take advantage of 2 or less processors. Hopefully Apple can get the pre-emptive multitasking on OSX up so that anything could run on the full 32 processor palette.

[mischief]

I may be way off here, but the IBM article mentions the 750FX having sub-unit split-out capability in both the processor architecture and the on-chip cache. It goes on to discribe how software could adress those "floating" subunits as separate, independantly oscilated units for the purposes of on-chip parallelling similar to altivec. It appears to me from these statements that rather than just a vector processor that splits down with a 32 bit stream from the bus THE WHOLE CHIP could be split down to accomodate parallel processes at differing clock speeds with different, pre-allocated cache space. There was also mention of a sub-processor running at up to 256 bit wide. This is much more than simply a 64 bit wide G3. The chip is on-the-fly configurable by software.

Please, Take your own analysis and let's see if we can't find all the implications here. We musn't ignore the fine details if we are to understand what has been done.

[KingArthur]

I had wondered if the processor may have an engine built-on that would automatically partition blocks of information so that it could use almost the full bandwidth of the pipeline. With a 128 or 256-bit subprocessing engine, the efficiency of the processor would be unparalleled in the market.

I thought that I knew what I was talking about with the 32 processor support. And just because no programs are spacifically written to divide work among more than two processors, the OS would still assign programs to a given processor. A quad-processor design would basically give one processor to the OS, two almost completely unused processors for your Photoshop rendering, and still leave one open so that you could run a couple other every-day programs on the final processor, all without SIGNIFIGANT slowdowns to your Photoshop or other programs. Although it is not quite that simple and there would be minor slow-ups to the system and other programs, it would be MUCH better than just two processors. And think of the possibilities if Photoshop and various other applications had future versions that supported more than two processors at once. That just gave me an idea::D What if the reason that Photoshop and some other graphics programs have not been ported to OS X because they knew something about the G5 that we don't and they are just taking the extra time to write in a Coco version that supports 64-bit processing (with whatever other enhancements might be on the chip)? That could be a logical conclusion about what the hold-up is (although not REALLY likely). I still will bet that the G5 will be released in MW July or later.

Well, I have to get back to reality now, so I bid you all a goodevening.


-------------------Your Sovergn King, Arthur-----------------------------

[mischief]

But it does tell me I'm not that far off.:D

[Unregistered]

Originally posted by KingArthur
I do have a question, though: OS X can automatically utilize the vector processing on certin operations that it recognizes right? So wouldn't it be logical that Apple would build in an emulator in OSX so that 64-bit processing may be utilized more? I do realize that a many applications would have to be rewritten to utilize 64-bit processing fully, but is there not something that could be done to the OS also?

First question: I'm not sure what you mean by "recognizing certain operations." OS X does "automatically" use Altivec in the sense that many components of the OS are Altivec accelerated. For example, I'm sure that Quicktime has some Altivec optimizations, and I believe Open GL does as well. Thus, any 3rd party application that calls Quicktime or Open GL will automatically get at least a little bit of a benefit from Altivec. Likewise, the window manager also uses Altivec. So most apps, not just the Finder, should have more responsive windows on a G4 than a G3 (since most should be calling the window manager). So in that sense, OS X automatically utilitizes Altivec. But it is not able to take 3rd party code that could benefit from vectorization and automatically vectorize it so that it can take advantage of Altivec - that would probably be nearly impossible.

Second question: I don't know if this would be possible (I would assume not), but the real question is what would be the point? The only thing that you need 64-bit words for is working with really large numbers. Most people don't have any need to do that. You could store all of the numbers in 64-bit words instead of 32-bit words, but it wouldn't be any faster (in fact, it might be slower in the sense that you'd probably need more transistors to implement all this 64-bit processing). Are you as a human being able to do math faster by adding 000100 + 000050 instead of 100 + 50? I doubt it, and guess what, it's not much different for a computer. I think there's a "bit myth" running around that's sort of like the "megahertz myth" - more bits is not necessarily faster (or even any better), just as more megahertz is not necessarily faster.

Third question: Well, I guess that's pretty much answered above. The bottom line is, most apps don't often use 64-bit integers, so what is the point of rewriting them? Certainly some could use 64-bit addressing (to access more than 4 GB of RAM)...I don't know how much, if any, of a rewrite that involves. Incidentally, I think the current G4 and such already allow for 36-bit addressing or something like that (yes, that is 36, not 32), but I have no idea how that works.

Just FYI, I'm not like some CS expert or anything - I'm an Economics PhD student. There are millions of people more qualified to answer these questions than I am. But I guess most of them don't visit these boards. ;-)

Mike

[Ossa]

Originally posted by KingArthur
That just gave me an idea: What if the reason that Photoshop and some other graphics programs have not been ported to OS X because they knew something about the G5 that we don't and they are just taking the extra time to write in a Coco version that supports 64-bit processing (with whatever other enhancements might be on the chip)?

Sorry to dissapoint but Photoshop has been ported, announced in Jobs last keynote speech.

[kansaigaijin]

Just FYI, I'm not like some CS expert or anything - I'm an Economics PhD student. There are millions of people more qualified to answer these questions than I am. But I guess most of them don't visit these boards. ;-)

Mike [/B][/QUOTE]
I acknowledge it is possible to be a polymath, but
these boards are too full (I dont mean you, particularily) of speculation people should base their purchasing planning on what they know they need. I wouldnt buy any brand new Apple product, wait six months, you will get something faster and cheaper, let someone else ride the bleeding edge. There are some good reliable consignment shops and sellers of refurbs,
So why feel compelled to answer the question, if you "believe" rather than "know". What will return Argentina to stability? Should other countries consider pegging their currencies to the dollar?
You are probubly right about the chips though, I think your best point is that few people actually need that kind of processing power.

[KingArthur]

I meant that we may see a Coco Version, not Carbonized like this one. That MAY have been a hold-up (although not likely). They might have been too busy with writing in Coco Apps.

Thanks, Mike, for your input. You seem intelligent and at least fairly reliable.

[oldMac]

Let's all thank Mike for clearing the air on what Alitivec does.

The power of Altivec is its ability to perform a single operation on several pieces of data at the same time. It's very powerful for processing a "stream" of data where the same operation is being performed on each element that comes through the pipe. Having wider Altivec registers would likely improve performance for a number of applications.

Let me chime in by saying that the "Megahertz myth" is a mild fallacy compared to the riduculous marketing hype of "32 bit, 64 bit, 128 bit, etc.". Thank the game console marketers for misleading the public in a massive way with regards to the "bitness" of their machines.

For those uninformed, 99% of the time, the "bitness" of a computer or console is a completely fabricated indicator of performance. Many console manufacturers are even referring to different things when they refer to their "128-bit" architecture.

[mischief]

There is mention of dynamic splitting of data paths. It is not directly stated but referred to in several places for a variety of reasons. I would like better analysis of these references than I can generate on limited knowledge. Please read it over again and lets get into the meat of the details.

[KingArthur]

The 256-bit wide idea given in the article is that the L1-Cache can recieve 256-bit wide data chunks. It does not mean that it can process 256-bits at a time. It does tell that the processor can handle 2 sets of data at different clock speeds, but that would help if you have one slower process, it would not hold up processes that can go faster. That could also be implemented into power-saving features in laptops; cutting off one of those paths to save power or keeping processes running as slow as possible. It would be a more primative type of AltiVec, but you never know if it may have special features like AltiVec. Now the part about 16 bats just allows more customizable and expandable systems. That is my interpretation of this. I do know that there will be a performance increase thanks to the refined copper-transistor technology.

[Catfish_Man]

...about Intel's Itanium that gives it such high performance? I know it's 64 bit, but as the posts above say, there's no reason why that should make a large performance increase.

[Catfish_Man]

...of getting more performance out of a 64 bit chip, would be to have the whole chip work like Altivec and accept 2 32 bit words at a time. It would require programs to be written to take advantage of it, but it would basically be like a mini-Altivec for non vector operations. If the program didn't have the type of operations that use SIMD then it would give any improvement.

[mischief]

Originally posted by Catfish_Man
A 64 bit chip would.... work like Altivec and accept 2 32 bit words at a time. It would require programs to be written to take advantage of it, but it would basically be like a mini-Altivec for non vector operations. If the program didn't have the type of operations that use SIMD then it would give any improvement.

That's exactly my guess. If you can ***ign sub units by speed to reduce power, there's no reason NOT to use it for splitting the data path.

Effectively IBM has built a 2 core, bridgeable, on-the-fly throttleable paired 32 bit G3 at half the power consumption of G4 and a 256 bit wide L1 cache that can also be ***igned in chunks on the fly.

(pant, pant......What a mouthful!)

Indications are that G5 is more multi-processor friendly, so 4 two-on-one-chip, Ghz, bridgeable G3's. That's SICK. Stick that on a 200Mhz bus with 4 Gigs and Itanium looks like a toy.

[Catfish_Man]

What 200MHz bus?! Every rumor I've heard about the G5 has said a 400MHz bus like the P4.

[mischief]

Shows a 200Mhz bus and design tolerance for up to 20 times the bus speed:

Once the Heat issues level out with the basic circuit tolerances we'll see 4Ghz G5's at 200Mhz bus 64 bits wide, splittable.

This is a thermonuclear hand grenade for the desktop.:D

" I spit on your puny, girlie P4."

" I'll soak your 10 D6 mace and hit you with my 10 D20 walking stick.......When the Character description says {GOD} in the Species slot, don't pick a fight.":D :rolleyes: :cool:

[Catfish_Man]

...is NOT the G5. It's a G3. A new, spiffy G3, but still a G3. No SMP. No Altivec. PPC 750 series core. The G5 is a Motorola project. With Altivec. With SMP. 8500 series core. The 750fx (Sahara) is awesome, but the G5 will crush it. Badly.

[mischief]

So the links to Sahara labelled as G5 were misleading. Do you have a link to G5?

If that's just Sahara......EEK!!

Sahara is ugly enough to make Apollo look kinda skimpy. Perhaps we will see Sahara in iBooks, Apollo in iMac and TiBook and G5 in Towers by the end of the Year.

[Catfish_Man]

...consists of the 750, the 750cx, the 750cxe (current non-G4 iMacs), and the 750fx (not in ust yet.)

[mozez]

guys, you're getting alittle caught up in rumors. there will be no 4 ghz g5. yes the new g5 has a 200 mhz bus, see the p4 actually runs two buses, each being 200mhz and for sales reasons they market it as a 400mhz bus, very misleading since the two buses screw themselves and rarely work together making a bottleneck. this is why apple choose to stay with one fully sped bus that works correctly. however, seeing how the main core will be an amd, that's right an amd design, apple has licensed the quadspeed architecture from amd as has cryrix and other board manufacturers. with this in mind and the fact the ddr ram chipset is a via take off and generally runs along the bus of an amd 266 bus better, they may improve intel's 200 mhz bus to match the ddr 2100 which runs at 266mhz. 64 bit will allow for over 2 gigs of ram and applications to take more advantage BUT as with the altivec engine, it needs to be optimized for that, you wouldn't believe how few programs are actually 64 bit, most are still 32, so it barely matters. the g5 will not, please note this people, it will not surpase whatever speed mark intel wants to come out with, they already have a 3.5 ghz chip, except for the fact it needs a mini ac to run, but if they even hear a rumor of something faster, trust me they will release a faster chip, they don't release till they need to. it doesn't mean they are faster, it just means the sheep of pc buyers will look and say oh bigger number, must be faster. the new g5 will do the same thing the g4 did, it will improve, it will be faster, better, all of those nice things, but it will not destroy boundries, marketing plays a roll here people, why jump out with something you can't follow up to, you send out you're fastest thing and the next week people are looking for more. try to think of this in video game terms, nintendo 8 bit, then 16, then genesis matched it, then they went 32 and other companies did and they all went along and then 64 and then so on, so look at it this way, nintendo, xbox, ps2, = apple, amd, intel, it runs like a scheduale and there are reasons why, would you buy a super nintendo if the ps2 was out at the same price? so why jump to a 4 ghz when all you have to match is 2 and when your customers don't expect you to jump so far, they expect ghz range, to mid 1.5 to 1.6, that will sell, then they can continue from there. be realistic about things. i'm sick of the people who go nuts and overboard and really think they know what they are talking about just by reading rumors. know the business side behind everything, it plays a bigger part than you think, and check other companies that have good ideas, because even though apple doesn't talk about alot of the places they get hardware and software ideas, the companies they get them from love to play it for all it's worth.

[mozez]

one last thing, just because you have the technology doesn't mean you will use it right away, timing is key and during a down time, surprises come in handy. and just becuase ibm or others talk about chips, doesn't mean that others get to use them or that they are even ready, if you check ibm things like a flat crt came up, that's right, two guys made a flat crt that is 2 inches thick and much much cheaper than flat panels, and, can be made in much bigger sizes, but you don't see it on best buy's shelf yet do ya. that was months ago too. so, my point here is, think what is smart for apple, not what you dream about. motoroloa could have 5 ghz chip it wouldn't matter, you make more money by going in stages and using timing to your advantage.

[MrMacMan]

You just blew my mind man.... :(
help... just how many differnect processors is the mac going to have at one time? 4? 5? more???
Wow we all now know why apple processor are slower in clock spped right?
That all made sense to all of you who have college degrees in engieering right???
:eek:

[krossfyter]

macman macman macman....

wakawakawaka...

[KingArthur]

That comment about P4s having 2, 200Mhz busses is not ENTIRELY accurate from the reading that I have. The P4 actually has a pipeline stage, the Arithmetic-Logic Unit operations (simple integer and logical ops) that can effectively run at double the bus speed (400 Mhz). Everyone should go to arstechnica.com because you can find the best database on the structure of the P4, the G4e, the K7 (AMD duron), and other processors.

I must admit that the P4 has some very revolutionary techniques, but sadly Intel kills the chip by using the narrow and deep approach to the processor. I love the idea of decoding instructions and predicting the branches before putting them onto the L1 cache. This actually reduces the number of pipeline stages, but when the level 2 cache is drawn from, it adds another 8 stages to decode and predict (which is understandable although excessive). I did my own calculations and in theory, the P4 running at 2.2ghz gets information off of chip about the same speed as the G4e running at 867Mhz (when you divide the 867 by the 2200 (for comparitive speed) and multiply that by the number of stages (20 in the normal cases of the P4)). The P4 goes about as fast as an equivilent 7.2-7.5 stage G4e. Now this would be in theory, but there are many other factors that speed the P42.2Ghz past the G4e867Mhz.

[Xeri]

Originally posted by KingArthur
The P4 actually has a pipeline stage, the Arithmetic-Logic Unit operations (simple integer and logical ops) that can effectively run at double the bus speed (400 Mhz).

The ALU pipeline stage(s) you refer to run(s) at twice the frequency of the CORE, not the BUS. There is a HUGE difference here. The bus and the core are pretty much completely decoupled in modern microprocessors outside of frequency ratios.

I believe I've heard the P4's data bus is double-pumped. This is probably what people are referring to.

[Xeri]

Originally posted by Catfish_Man
...about Intel's Itanium that gives it such high performance? I know it's 64 bit, but as the posts above say, there's no reason why that should make a large performance increase.

The architecture of the IPF (Itanium Product Family) is completely different from other superscalar RISC processors. It is generally referred to as VLIW (Very Long Instruction Word) or EPIC (Explicitly Parallel Instruction Computer.)

Instead of having several execution units hidden behind some layer of out-of-order issue circuitry, IPF instead lays the processors execution pipelines out for more direct access by the software writers. IPF handles bundles of up to three instructions at a time. In theory, this could enable up to 3x the intruction throughput of other current microprocessors that only retire one instruction per cycle. (In reality, NOPs and instructions that are predicated out of existence reduce this number.)

The downside? Compilers get extremely messy because now THEY get to deal with the complexity of managing the hardware that used to be handled by the hardware itself. IPF is still heavily in the early stages of development for these sorts of compilers. It remains to be seen if the gamble of the new architectural approach pays off.

Oh did I mention that these are presently incredibly power hungry (as most new architectural implementations are)? I'd expect the IPF to stay in the high-end workstation and server space for awhile.

[-=AsukA=-]

whats all this talk of 200 MHz system bus speed? the G5 is definetly 400MHz Bus speed! yeas were talking about Mac MHz (up to 2 times faster that PEE CEE MHZ) so that mean the Pentium 4s day in the sun is numbered!

dont believe me? look for your self: http://www.theregister.co.uk/content/39/21692.html

[Smasher]

Originally posted by -=AsukA=-
whats all this talk of 200 MHz system bus speed? the G5 is definetly 400MHz Bus speed! yeas were talking about Mac MHz (up to 2 times faster that PEE CEE MHZ) so that mean the Pentium 4s day in the sun is numbered!

dont believe me? look for your self: http://www.theregister.co.uk/content/39/21692.html

That's the same Register article that's been widely discredited. If you look at the date of publication, it was put out in September, more than four months ago, and that's assuming it actually had something to it to begin with, which it apparently didn't.

[KingArthur]

I meant to say that the ALU is double-pumped, but accidently wrote the wrong info. But the ALU did get a lot of hype, and that is what I think this 400Mhz P4 bus thing comes from. The one funny thing about this ALU is that it is not well-fed; therefore it frequently wreaks havok with bubbles. Branch mispredicts kill it. The information that I have been reading-up on has provided me with a greater knowledge of how these processors actually work.
Quite facinating.

[swatara]

Howdy -

Some information on the P4/P4 Xeon/P4 Xeon MP bus- It is a split transaction (pipelined, packet based) bus. The _data_ rate _is_ 400Mhz. Data is transferred on the data bus in 8 byte chunks (8 8 byte chunks give you a 64 byte cache line), so if the data bus is fully utilized and you have a 100 Mhz front side bus (data bus is quad pumped), you can approach 3.2 GB/sec. Many of the bus strobes (control signals) run at 100 Mhz. One drawback to the shared FSB approach to SMP is that all the processors on this bus share the same bandwidth. One positive to this approach is that it is very easy for other processors on the bus to "snoop" on transactions by other processors making the cache coherency protocol a little easier to implement. So if you are trying to implement a memory controller/northbridge or whatever you want to call it, you want to make sure that you can support the kind of bandwidth that the processor can demand. In a server type system this usually means multiple DRAM channels and very wide data paths in the memory controller. Otherwise you run the risk of starving the processor for data which obviously has performance implications.

As far as 64 bit processors go there are several benefits. One that was mentioned here is being able to address more memory and/or increase the amount of virtual memory that you can address. I.e. 64 bit pointer types. The main use of these (besides more precision for number maths) is for sparse databases. If you want to maintain a large database or do data mining or scientific applications you may need/want this capability. The average home user is usually not going to need this kind of precision or capability for running their spreadsheets or surfing the web, but if you are into scientific applications or are planning on running a big database, they are nice.

Hope this is informative,
Swatara

"What can change the nature of a man? Regret..."

[anshelm]

You are right except for one technical error you made. MHz is not data rate. That's bandwidth. MHz is a measure of the frequency. That is ALL MHz is a measure of. Hz is the SI unit for cycles per second. Therefore, it is a 100MHz system bus that is quad-pumped that has the bandwidth of a 400MHz bus. But that doesn't make the frequency of the bus higher. It makes it transfer data at the same speed overall as a 400MHz bus that is single pumped, but it does not make the 100MHz quad pumped bus a 400MHz bus.

Bandwidth is the data transfer rate. MHz is the frequency rate. Having a bandwidth equal to that of a higher-frequency bus does not make your bus have that higher frequency.

[swatara]

Hello-

I made no technical error.

Bandwidth is the amount of data that is transferred in one cycle.

Bandwidth = frequency * width of bus in bytes. I.e. a 100 Mhz bus that is 8 bits(1 byte) wide could have a theoretical peak bandwidth of 800 MB/sec. So a 400 Mhz bus 8 bytes wide has a theoretical bandwidth of 3.2GB/sec if the bus protocol and memory controller are good enough to keep the bus busy.

How do you think that data is sent on that bus? It has to be clocked, its just not asyncronous between the two devices. In this case it is a source syncronous design where the memory controller or the processor drives two, 200Mhz clocks that are 90 degrees out of phase. What it boils down to is that the data is clocked on both edges of a 200Mhz clock - sort of like DDR Dram. The data bus _IS_ 400Mhz. I should know, I have the Intel P4/P4 Xeon/P4Xeon MP orange documents sitting right in front of me. :) These are not new design techniques..

BTW, I'm not posting these because I am a Mac hater or POWER/PowerPC hater (I am a Computer Architect/ASIC Designer for IBM)... I just have happened to work on memory controller designs for both Power4, IA-32 Foster, and the follow on to the IA-64 Merced(now known as Itanium). Believe me, it would be great to see Macs use GP(Power4).

Regards,
Swatara

[anshelm]

SDRAM itself is asyncronous. So, to make it so the processor and the RAM can talk, they sink it to a bus clock cycle.

The "400MHz" claim is because of two 100MHz bus operating in the same way of DDR SDRAM. DDR sends two packs of data per clock cycle, on one the up, and on the down.

That doesn't make the clock frequency any higher. It means you can transmit twice as much data at the same frequency as before.

Bandwidth on a SINGLE pumped system is "Bandwidth = frequency * width of bus in bytes". However, on a double pumped bus you have to multiply it by two, because it can send TWICE as much data at the same frequency.

But the FREQUENCY, the clock tick, is THE SAME. I would hope, since you are a system architect, that you would know this. Browse over to arstechnica for some more in-depth explainations.

[anshelm]

"The _data_ rate _is_ 400Mhz"

If you mean that the data rate is equal to that of what you can transmit on a 400MHz bus, you're right.

But, if you mean that the actual data rate is 400MHz, you're wrong.

400MHz isn't a data rate. 400MHz means the clock cycles 400 million times per second. But even Intel admits that it's a 100MHz bus.

3.2GB/s is the data rate. The quad-pumped (I know it's two buses, but Intel intends for them to act as one, so I will use their explaination) 100MHz bus has the same DATA THROUGHPUT as a 400MHz bus... but it's a 100MHz bus.

When I say that the bus is 100MHz, I mean the clock cycle. The frequency. But DDR and RDRAM allow us to double what you can do with the frequency. So the bandwidth is equal to that of a doubled frequency. But that doesn't make the frequency itself equal to that of the higher frequency.

[anshelm]

"What it boils down to is that the data is clocked on both edges of a 200Mhz clock - sort of like DDR Dram"

I think I see our misunderstanding:

We both agree that the data that can be transmitted is equal to that of the higher frequency.

But what we disagree on is calling it 400MHz. Yes, the data gets transmitted at the same rate as it would on a 400MHz clock cycle, but it's on a 100MHz clock cycle. (I think I just don't like fudging things. To say it's a 400MHz bus implies that you could then double pump it to get the equal data transfer rate of a 800MHz bus.)

Part of the problem that I think is confusing everybody (not you, I mean people in general) is that electricity goes no faster in a 66MHz or a 133MHz bus setup. The electricity takes just as long to reach point B from point A. It's just with a higher frequency you can have more peaks per second, so you can transmit more data each second, so you can transmit files faster because it doesn't have to wait as many seconds for enough peaks (and width double-pumped buses, it can send twice as much data on the same clock).

Anyway. I hope nobody's upset about my amount of posts, I was just trying to make my point clear. (If anyone is curious what I'm trying to say, browse over to a page on my site http://jeni-lee.com/anshelm/rants/fsb.html. Note: requires Flash 5 plugin)

[StealthRider]

Why does my G3 B/W seem faster than a 500 MHz Pentium 3, even with no Altivec....?

[eyelikeart]

because it is.... ;)

[LordRPI]

Those rumors you're hearing about IBM and the G5 without AltiVec... can you guys be mistaking these with the IBM Power5?

[Catfish_Man]

...at IBM's PPC roadmap. The next processor on the list is dual core, 1GHz+, integrated SIMD engine (sounds like Altivec to me), .13 micron. The one and only place that might clash with our current info about the G5 is that it doesn't say whether it's 64 bit or not. We've been assuming that the G5 will be the Motorola 8500. It might not be.

P.S. Think about this: Assume that the G5 (the IBM one) gets the same amount done per clock pulse as the G4 (longer pipeline, but faster bus and smaller wires). Assume that the rumors we've heard about its clock frequency are correct (1.6GHz top). That would mean that ONE core of the dual core chip would be twice as fast as the current 800MHz G4. Since it's a dual core chip it would be close to 4 times as fast. If you had a dual processor version of it, it would be getting somewhere near 8 times as fast. Somehow I doubt they're going to release a DP version of it first, but it's fun to think about :)

[KingArthur]

Sorry to keep reverting back to this data-rate thing, but since anshelm mentioned arstechnica, I couldn't help myself. Now, since you have read the articles, you would have read that the ALU IS AT DOUBLE THE CORE FREQUENCY!! I read it twice in the last two days. Frequency is measured in hertz (cycles/unit of time) and bandwidth is measured in bits/cycle (Mbps). The P4 has two double speed ALUs which in theory would do the job of four regular ALUs; but we all know that unless you keep the ALU fed with data, it has less of an effective speed. The P4 also has a third ALU for complex operations like multiplication and division which runs at core frequency and usually takes anywhere from 15-45 cycles to complete.


Hey Swatara; I am really getting into the archetectural designs of CPUs and was wondering if you would know of any really good sources of info on CPUs (not just G4 and P4, but also any AMD processors and ones like the G3 and P3 and P2 (aka celeron)). Give me an e-mail if you would be so kind.

[KingArthur]

Oops. I forgot to reply to your response Catfish_man.

I believe that if we are correct in judgements of this being the correct processor, then yes, the SIMD would be AltiVec (or another name). We may even see a newer SIMD that integrates not only into Vector processing but into FlotingPoints and/or other various elements. This would definately be an advantage and innovation which would stun the market. It would be quite hard to program for a SIMD FPU, though, because of all the conditionals needed to be processed.

[Catfish_Man]

Originally posted by KingArthur
Oops. I forgot to reply to your response Catfish_man.

I believe that if we are correct in judgements of this being the correct processor, then yes, the SIMD would be AltiVec (or another name). We may even see a newer SIMD that integrates not only into Vector processing but into FlotingPoints and/or other various elements. This would definately be an advantage and innovation which would stun the market. It would be quite hard to program for a SIMD FPU, though, because of all the conditionals needed to be processed.

...that you're misunderstanding vector processing a bit. A vector is a group of floating point or integer variables. Altivec can do either floating point or integer math, but only on multiple variables at the same time. Most of the info on processors that I have is from http://www.arstechnica.com . I know that's where the G4 v P4 article is, but they have some on the Athlon and Itanium procs too.