2.5 GHz PowerMac G5 Dev Notes

[Sun Baked]

The 1.8, 2.0, 2.5GHz PowerMac G5 Dev Notes have been posted -- and they show some interesting changes.

Since Michiro has already found most of them, I'll not retype them.

Originally posted by M.Isobe:
_New Power Mac G5 Developer Note_

Apple posted new Power Mac G5 developer note (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/index.html).

Do you remember my report (http://episteme.arstechnica.com/eve/ubb.x?a=tpc&s=50009562&f=8300945231&m=9080959175&r=321009974631#321009974631? ) The document proves that dual 1.8GHz model is very different (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/2Architecture/chapter_3_section_2.html#//apple_ref/doc/uid/TP40001397-CH206-BCIDGEEE) from other models (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/2Architecture/chapter_3_section_2.html#//apple_ref/doc/uid/TP40001397-CH206-BCIHCCCI).

* Dual 1.8GHz model uses "U3" memory controller and other models use "U3-H" memory controller, which is the same version with Xserve G5,
* Dual 1.8GHz model does not have HT-PCI bridge chip. The expansion slots are connected to the PCI interface integrated in K2 chip.

Although dual 2.0GHz and dual 2.5GHz models use U3-H memory controller, they do not support (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/4Expansion/chapter_5_section_2.html#//apple_ref/doc/uid/TP40001397-CH208-TPXREF103) ECC DIMM. _Important_
DIMMs with any of the following features are not supported in the Power Mac G5 computer: registers or buffers, PLLs, ECC, parity, or EDO RAM.The only improvement of U3-H memory controller is 1200MHz high-speed HyperTransport 2.0 (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/2Architecture/chapter_3_section_5.html#//apple_ref/doc/uid/TP40001397-CH206-TPXREF132). The HyperTransport bus between the U3H IC and the PCI-X bridge is 16 bits wide, supporting total of 4.8 GBps bidirectional throughput.One big disappointment is 970FXs in dual 2.5GHz model don't use PowerTune technology (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/1Overview/chapter_2_section_5.html#//apple_ref/doc/uid/TP40001397-CH205-TPXREF110). _Processor States_
The following processor states are defined:
- Run: The system is running at maximum processing capacity with all processors running at full speed.
- Idle: The system is idling; this is the default state. All clocks are running and the system can return to running code within a few nanoseconds. If the system has no work to do, it will be in idle mode.EDIT: Regarding the PowerTune comment -- Here is IBM's document Improvements in power management techniques in Power Architecture (http://www-1.ibm.com/technology/power/newsletter/june2004/article8.html)

[Sun Baked]

I guess this answers quite a few of the New DP 1.8GHz G5 (block diagram) (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/art/040177001721_01b.gif) versus Old DP 1.8GHz G5 (block diagram) (http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5_Nov03/art/03107301P1724_01.gif) questions.

[2A Batterie]

I might have well tried to read sanscirt too. I'm a dummy, so all I want to know is if the new G5's all use the 970 or 970fx. Is there really that much difference between revA and B? Are there wider data paths?

[ddtlm]

2A Batterie:

Are there wider data paths?
No there aren't, nor are wider paths needed at this time. What is needed is a lower latency memory system such as on-die memory controllers and more L2. Looking at the performance of a 2.5ghz G5 vs a 2.0ghz G5 it seems to me that scaling is always well below the 25% clock speed increase, even in Apple's posted benchmarks. That's a sure sign that the processor isn't getting the data it needs despite the impressive looking FSB.

I think Apple's best bench (Bibble 3.1a) shows the 2.5ghz G5 at 150% faster than a P4 vs 119% for a 2.0ghz model. So relative performance is (100+150)/(100+119) = 14% boost.

But anyway, thats off the topic. On topic, I'll also be very interested when it is definately settled what sort of 970 is in the lower-model PMacs.

[Sun Baked]

>ddtlm

Compare this old M. Isobe 6-19-2004 report to the Dev Note:

New machines are the mysterious PowerMac 7,3

The PVR of the new DP 1.8 & 2.0 was for the 970 (130nm), not the 970FX (90nm).

The KeyLargo2 was updated in all the machines tested.

The DP 1.8 had the original U3 System Controller (aka slower HT).

The new DP 2.0 had the XServe U3H System Controller (aka faster HT, and ECC memory capable), but isn't using ECC memory.

[Sun Baked]

[deleted]

[Mac Maven]

I apologize for replying to this old thread, but I am wondering why Apple has always chosen not to use the various forms of error checking including, most recently, ECC. The support is built into the U3H memory controller of the (Rev B) 2.0 and 2.5 but goes unused. The Xserve uses the same memory controller requires ECC RAM. I don't think the price premium for ECC RAM is that much of an issue. If higher end PCs have used error checking for such a long period of time, why do Power Macs continue not to? It's not really a big issue, really more of a curiosity to me. I just learned today the difference between the U3 and the U3H, and that a main distinction is the significantly higher amount of heat produced by the U3H. I know that the U3H is required because of its faster rates for the DP 2.5, but I don't understand what benefit it is to my DP 2.0. Without ECC the only thing the U3H seems to do for DP 2.0 owners is register high temperature levels. Hopefully someone can give me other reasons for having the U3H. Overclocking is perhaps one possibility, but I'm asking about what extra benefit it provides to a stock machine.

[daveL]

I apologize for replying to this old thread, but I am wondering why Apple has always chosen not to use the various forms of error checking including, most recently, ECC. The support is built into the U3H memory controller of the (Rev B) 2.0 and 2.5 but goes unused. The Xserve uses the same memory controller requires ECC RAM. I don't think the price premium for ECC RAM is that much of an issue. If higher end PCs have used error checking for such a long period of time, why do Power Macs continue not to? It's not really a big issue, really more of a curiosity to me. I just learned today the difference between the U3 and the U3H, and that a main distinction is the significantly higher amount of heat produced by the U3H. I know that the U3H is required because of its faster rates for the DP 2.5, but I don't understand what benefit it is to my DP 2.0. Without ECC the only thing the U3H seems to do for DP 2.0 owners is register high temperature levels. Hopefully someone can give me other reasons for having the U3H. Overclocking is perhaps one possibility, but I'm asking about what extra benefit it provides to a stock machine.
No idea on the ECC issue. It's used in the G5 servers, but the not the desktops.

I doubt the U3H runs hotter in a 2.0 GHz G5 rev. B. The added thermal output is due to the faster (1.25 GHz vs 1.0 GHz) FSB on the 2x2.5 GHz PM. If your FSB is running at 1 GHz, there's no reason for any significant increase in heat on your machine.

[Sun Baked]

Without ECC the only thing the U3H seems to do for DP 2.0 owners is register high temperature levels. Hopefully someone can give me other reasons for having the U3H. Overclocking is perhaps one possibility, but I'm asking about what extra benefit it provides to a stock machine.The U3H also include a upgraded HT interace, so the bandwidth moving over the HT Bus is increased.

A boost to 4.8 GBps on the U3H from 3.2 GBps on the U3.

ECC and a HT change were the two major changes we saw as consumers, but Apple doesn't release information on what other changes they may have made.