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Sun Baked

macrumors G5
Original poster
May 19, 2002
14,937
157
Originally posted by M.Isobe:
_Power Architecture Community newsletter, Issue #2_

IBM posted Power Architecture Community newsletter, Issue #2. The most interesting article is "Power envelope and power management in Power Architecture processors". The article describes max./min. power and voltage of 970FX/2.5GHz.
The reduction in frequency from 2.5 to 1.25 GHz to 625 MHz reduces the power from _100 to 75 to 60 W_. At f/2 and f/4, a decrease in voltage can further reduce the power. The amount of power savings is dependent upon how far the voltage can be reduced. If the voltage can be reduced to 0.8 V, the power could be reduced to 15 and 10 W at f/2 and f/4, respectively. _Today, a functional limitation exists in the 90-nm design, preventing operation below 1.0 V_. This raises the lower edge of the power envelope from 0.8 to 1.0 V and the lower power line in our example to 27 and 19 W for f/2 and f/4, respectively. _At the same time, the 1.3-V application condition can only be applied to products with <50 000 power-on-hours (POHs)_. To accommodate the reliability requirements of a 100 000-POH system, the upper voltage must be limited to 1.2 V .
The article also describes the effect of leakage and the dispersion of it due to the individuality of chips.
Figure 1 shows the total power of the processor and these three major components as a function of line center, where line center is the dimension of the transistor's gate. As the transistor is printed smaller or at a more negative sigma, the speed of the processor as well as the subthreshold leakage current increase.
and...
Originally posted by M.Isobe:
Above article indicates current situation of 970FX.

* The reliability problem in high voltage (Vdd > 1.2V) operation inhibits faster (> 2.5GHz) chip.

* We cannot expect ULV revision for PowerBook because 90nm 970FX does not work below 1.0V.
 

Sun Baked

macrumors G5
Original poster
May 19, 2002
14,937
157
As stated by others, looks like he found more cool stuff.

like this IBM graphic on the 2.5GHz PPC970fx...

Figure 2. Maximum power envelope from 0.8 to 1.3 V showing the power reduction possible through power-tuning methods.

article7_2.jpg


Figure 3. Maximum power and nap power envelopes showing transitions from maximum power to nap power at f, f/2 and f/4, and then to deep nap at f/64.

article7_3.jpg


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But the compromise in POH reliability the for the 2.5GHz PPC970FX is quite interesting. :eek:

Plus this chip is "supposed" to be as miserly as the old 1.8GHz PPC970 which had a "typical" of 50W -- and we now see a max here of 100W. ;)
 

MacinDoc

macrumors 68020
Mar 22, 2004
2,268
10
The Great White North
Sun Baked said:
Plus this chip is "supposed" to be as miserly as the old 1.8GHz PPC970 which had a "typical" of 50W -- and we now see a max here of 100W. ;)
Didn't I read somewhere that the "typical" heat dissipation of PPC chips as quoted by Apple/IBM is usually about 1/2 of the maximum heat dissipation?
 

Celeron

macrumors 6502a
Mar 11, 2004
705
9
Sure thing.

Current the 970FX processor has the following problems:
1. It can't run with voltage under 0.8v because of a technical problem in the manufacturing process (0.90nm). The lower the voltage, the lower the power consumption, thus the lower the heat output. This is probably why you won't see a G5 Powerbook for a while.

2. It can't run reliably at voltages over 1.2. At 1.3v, the voltage required for speeds above 2.5gig, the reliablility of the processor goes down.

At least thats what I understand all the above mumbojumbo to be talking about.
 
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