and...Originally posted by M.Isobe:
_Power Architecture Community newsletter, Issue #2_
IBM posted Power Architecture Community newsletter, Issue #2. The most interesting article is "Power envelope and power management in Power Architecture processors". The article describes max./min. power and voltage of 970FX/2.5GHz.The article also describes the effect of leakage and the dispersion of it due to the individuality of chips.The reduction in frequency from 2.5 to 1.25 GHz to 625 MHz reduces the power from _100 to 75 to 60 W_. At f/2 and f/4, a decrease in voltage can further reduce the power. The amount of power savings is dependent upon how far the voltage can be reduced. If the voltage can be reduced to 0.8 V, the power could be reduced to 15 and 10 W at f/2 and f/4, respectively. _Today, a functional limitation exists in the 90-nm design, preventing operation below 1.0 V_. This raises the lower edge of the power envelope from 0.8 to 1.0 V and the lower power line in our example to 27 and 19 W for f/2 and f/4, respectively. _At the same time, the 1.3-V application condition can only be applied to products with <50 000 power-on-hours (POHs)_. To accommodate the reliability requirements of a 100 000-POH system, the upper voltage must be limited to 1.2 V .Figure 1 shows the total power of the processor and these three major components as a function of line center, where line center is the dimension of the transistor's gate. As the transistor is printed smaller or at a more negative sigma, the speed of the processor as well as the subthreshold leakage current increase.
Originally posted by M.Isobe:
Above article indicates current situation of 970FX.
* The reliability problem in high voltage (Vdd > 1.2V) operation inhibits faster (> 2.5GHz) chip.
* We cannot expect ULV revision for PowerBook because 90nm 970FX does not work below 1.0V.