Haswell mainstream Core i CPUs with integrated graphics? It is 4 cores. Ditto on the derivative Xeon E3 class models.
Haswell Xeon E5's have relatively high chance of being the same core budget as the Ivy Bridge Xeon E5's. A range of 4-8 (for 1600's ) and 6-10 (for 2600's) and arrive around 2014. There is no process shrink between Ivy Bridge to Haswell so likely keep the same core count since the transistor budget isn't going to grow that much. The big deal is more so DDR 4 memory and substantively improved micro-architecture. So 4-8 cores with faster throughput/"horsepower".
There are rumors of 14 cores with Haswell E5 ( '-EP' )
http://vr-zone.com/articles/idf-sf-...antley-in-2014-now-with-moar-cores/17188.html
But those seem a bit flawed on several fronts.
1) With no process shrink at all somehow there is a 4 core jump from Ivy to Haswell; a doubling of the past trends. (maybe better 3D layout gets 2 but 4? Where was all this space back in Ivy Bridge? Same size package so die size likely roughly the same. ).
2) I don't see how transactional memory (
http://www.realworldtech.com/haswell-tm/) is "ultrabook focused". I'd suspect that transactional memory to improve lock performance would have bigger impact on a 8-10 core system than one limited at 4.
3) There is lots of handwaving needing a "recompile" to get gains being a problem. Well, the bleeding edge Intel compilers would have been out for more at least a year before Haswell E5's arrive. There is going to be alot more Haswell optimize code around when the E5 class arrives than when the desktop class arrives a year (or slightly more ) earlier. AVX would have been around for at least two years. On code with heavy math computation loops the code will perform better. Unless committed to running Pentium 4 optimized CS2, there will be a bigger than 10% bump for most workstation/server class code.
4) There are significant changes to memory hierarchy in Haswell (
http://www.realworldtech.com/haswell-cpu/5/ ) that have a good chance of having more impact when coupled to DDR 4 (and context of math oriented workloads: AVX, SIMD, dp float loads , etc. ) than to the mainstream's coupling to DDR 3 and 2 channel memory starved workloads.
So the whole "the cores are weak but lower power so just pile more of them on the die" mentality just seems rather limited thinking for Intel to be following where scalar critical sections are going to be important. The Xeon Phi already does that with an even higher core count density oriented for more parallel workloads. The Xeon E5's should aimed at a different target than the Phi.
Fewer cores (10 versus 14 ) clocked faster would be better use of the power budget.
