Systems on a Chip like this are composed of functional blocks.
For example, one or more CPUs, one or more GPUs, timing, video, memory, high speed I/O and other circuit blocks.
(Many sections are composed of even smaller functional blocks ... eg. a CPU section will contain registers, cache, memory interface, etc.).
When people talk about customzing such systems, often it simply means picking and choosing the major blocks you want to include on the chip.
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What the article is saying, is that the layout indicates there was some manual intervention, which might be done to try to speed up certain connections by placing them closer together. (Even at electrical speed, distance counts.)
check this article:
http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core
it's believed that apple has implemented their own arm-compatible CPU.
this article just says that it looks like a custom layout. again, they're not going to place each and every logic gate and flip-flop by hand. there's too many. but, as pointed out earlier they may have layed out some flops and gates of the datapaths by hand. what you are looking at in that die photo is the result of floorplanning different blocks within the CPU to particular areas of the chip.
there are special design tools for laying out asics. you work on it iteratively, doing the floorplanning, placing some of the large cells (like PLLs, DLLs and internal memories) by hand in the graphical tool. you then take that layout and create a representation of it that the placer/router can understand, and you autoplace and route the design. you then extract the timing and all the parasitic capacitances and resistances from the routed design and "back-annotate" the gate netlist of the chip. (the gate netlist is sort of like a schematic - it's composed of logic gates and flip flops, rather than high-level code like verilog).
then, you do a static timing analysis of the back-annotated netlist to see if it can run at whatever frequency you need. if not, well, back to the layout to try to upsize buffers and fix whatever violating paths you have. if you can't get it to meet timing with layout tricks, you may have to make changes to the RTL and re-synthesize the design (which is something i didn't cover above)
if you find a bug in the logic while you're doing the layout, you may have to do an ECO, that is, edit the gate netlist itself to implement the fix. this is because the layout engineers may have done some hand placement and they don't want to start over again with a new synthesized netlist which could have different net names.
then you have to do all kinds of design rule checks to make sure that the placement and routing is actually kosher for the cell library and process rules you are using. finally, you "tape out" which means to send the layout of each layer of the chip to your fab, and they start making it.
that's a very simplified view. in reality you also have to do gate-level simulations of the back-annotated netlist to make sure the chip will really come out of reset and the PLLs will lock, etc. also like i said i didn't cover the actual logic design, which will be done in either Verilog or VHDL and synthesized into gates with Synopsys' Design Compiler or similar software. all of that comes before you use whatever tool you use to do the layout. oh, and you need to do formal verification between the RTL and the gates, and between the pre-layout gate netlist and the post-layout gate netlist, since logic can be inserted during the layout phase. you need to make sure that the logic is the same as the original design after you've touched it.
so yeah, apple sends this stuff to samsung and samsung fabs the chip. but if you think that apple's "just using" samsung's off the shelf stuff, you're wrong. at this point the A6 cpu core is a custom apple design. and even if they were just using library components for the CPU and everything else, apple engineers still have to do all the placement, timing analysis, etc. if the chip comes back a brick it's just as likely to be apple's fault as samsung's. all of the above stuff i've written is entirely on apple's plate.
it's a lot of work and it's work that apple has done, not samsung.
