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Old Jan 1, 2003, 07:27 PM   #1
arn
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Apple: MaxBus, ApplePI, RapidIO, Hypertransport?

There have been various rumors going around about these technologies... and to be honest, I don't have a great feel for them all... I was hoping to prompt some discussion on these technolgies and their prospects.

Now, Apple is said to be part of the Hypertransport Consortium which is also utilized in NVidia''s nForce2.

MacEdition posted about an upcoming Apple Processor Interconnect Bus that is supposedly being put together to work with the IBM Power 4 970.

Motorola's 7457 due in 2Q 2003 will have a 166/200Mhz Max Bus. (as opposed to the current 133/166Mhz Max Bus). I'm not familiar with this terminology.

Any thoughts?

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Old Jan 1, 2003, 09:19 PM   #2
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Well I hope we get some faster bus soon cause what we are one now AINT gonna cut it.
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Old Jan 1, 2003, 09:50 PM   #3
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Well, if the PowerMacs move to a 200MHz system bus while also increasing the cache size, we could see some nice improvements in the PowerMac line, without even upping the clock speed.
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Old Jan 1, 2003, 10:10 PM   #4
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970?

Doesnt the 970 support a 900 mhz bus? I am hoping we could get something along those lines if Apple goes IBMs way. a 200 mhz bus would suffice i guess, but i would like to see more bandwidth across the bus, as this is one of the current bottlenecks within the architecture. Just my 2 cents.
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Old Jan 1, 2003, 10:13 PM   #5
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Don't expect that 200mhz "Max Bus" until DDR-400 is mainstream (remember the mem-to-FSB ratio).

The "Apple Processor Interconnect Bus" is probably nothing more than rebranded technology that IBM is making, since (we can assume) all machines running PPC-970's would use the same sort of FSB.

I don't see much point in hypertransport for Apple, since their system controllers have recently been single-chip anyway (not much use for an interconnect bus when there is only one chip).
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Old Jan 2, 2003, 02:12 PM   #6
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Not RapidIO

Apple won't use RapidIO. The interface to the 970 will be propietary. I think the ApplePI interface sounds like the most likely candidate.

Apple isn't even a member of RapidIO:

http://www.rapidio.org/about/list/
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Old Jan 2, 2003, 03:09 PM   #7
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Never heard of MaxBus...

ApplePI, RapidIO, and HyperTransport are high speed chip to chip interconnect protocols

ApplePI (Apple Processor Interconnect) is rumored to be based upon HyperTransport (of which Apple is a consortium member). And supposedly the protocol in use on the IBM Power4 970.
This isn't exactly fact, but is not unsubstantiated. The Hypertransport bus on the upcoming AMD "Hammer" Athlon64 and Opteron is a 800MHz HT bus while the 970 is 900MHz isn't such a huge difference since HT can scale up to 1600MHz and some inconsistencies bring the actual bandwidth of the 900MHz 970 bus to the same bandwidth of the 800MHz bus of the "Hammer" at 6.4GB/s.

RapidIO is a Motorola developed protocol already in use in some of their designs. It is reportedly going to be used in future G4 incarnations according to Motorola roadmaps and will most likely debut at about 400MHz providing 3.2GB/s bandwidth.

Hope that clears it up for you.
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Old Jan 2, 2003, 03:36 PM   #8
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Yes, very good.
Now anyone want to put a guestimate (clever splice of guess and estimate) on these dates?
MaxBus --- Out
ApplePI ---- Very possible
RapidIO ---- May come out with Moto chips
Hypertransport ---- We may see Some kind of this come out around 970 chip.
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Old Jan 2, 2003, 03:39 PM   #9
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Just to add my $0.02, the IBM 970 has a DDR 900 MHz FSB (450 rising and falling) which should go nicely with DDRII. AMD just came out with a 333 FSB (166.67 x2) and is surely working on 400+. Intel uses the Quad-Pumped method (like RAMBUS), so they have 400 and 533 (100/133.33 x4) now and 666.67 and 800 (166.67/200 x4) coming later. All in all it should be a very interesting year for CPUs.

It would be nice to see the G3s and e/iMac G4s get a 133+ FSB. Especially if Moto has a chip capable of a 200 FSB. Although remember how long it took for Apple to actually implement the 167 FSB, even though the G4 had been capable of it for awhile.

If you want to know more http://www.arstechnica.com has a ton of info, although a lot of it is in heavy tech (geek) speak.
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Old Jan 2, 2003, 04:25 PM   #10
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Reality Check

Just a reality check:

-At 1.8ghz, which is the projected top speed of the initial 970, it performs like a 2.8ghz P4 on SPEC. Even if the wider memory bandwidth does some magic, we are looking at running at the equivilent of a non-HT 3.06ghz P4. Better hope they are cheap, Apple will need to use 2 in each machine to become competitive on performance. We will be up against 3.6ghz+ HT P4s running on 800mhz FSB, not to mention the Hammer brigade.

-ApplePI may have been the thing that helped to kill the 'G5' according to the reliable Architosh. It looks like a BIU to enable PPCs to run on HyperTransport, nForce-like mobos. If Apple did not need it, they would not have joined the consortium. It may enable Apple to rely more on partners like nVidia for mobos...Maybe Apple should have tried harder to get more out of Moto, even just real DDR support for the aged, inadequate G4.

-Many firms in Apple's target markets will want to upgrade and will not want what Ars Technica rightly called the 'overpriced embarassment' that is the current 'Pro' lineup. They will not be excited about 1.4ghz duals with fake DDR. They will buy PCs and not go back.

-The situation is dangerous. The 970 is our best hope, but Apple needs to spec machines like high-end PCs and go back to the idea that some will pay a reasonable, marginal premium over a higher-end PC to have a Mac. The price/performance gap is a peril for the long-term health of the platform if it continues.
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Old Jan 2, 2003, 05:09 PM   #11
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Quote:
Originally posted by solvs


It would be nice to see the G3s and e/iMac G4s get a 133+ FSB. Especially if Moto has a chip capable of a 200 FSB. Although remember how long it took for Apple to actually implement the 167 FSB, even though the G4 had been capable of it for awhile.
Isn't the Sahara G3 in the new iBooks capable of running a 200 FSB? I wonder why Apple has not started using this if IBM can do it.
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Old Jan 2, 2003, 05:48 PM   #12
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Quote:
Originally posted by ddtlm
Don't expect that 200mhz "Max Bus" until DDR-400 is mainstream (remember the mem-to-FSB ratio).

The "Apple Processor Interconnect Bus" is probably nothing more than rebranded technology that IBM is making, since (we can assume) all machines running PPC-970's would use the same sort of FSB.

I don't see much point in hypertransport for Apple, since their system controllers have recently been single-chip anyway (not much use for an interconnect bus when there is only one chip).
They could run DDR-266 @ 200 MHz. Using DDR as done now on powermacs & xserve is not really usefull, since the memory is twice the speed of the system bus. Of course it has some advantagous (sp?) but upping the system bus might be a bigger improvement.
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Old Jan 2, 2003, 06:00 PM   #13
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Re: Reality Check

Quote:
Originally posted by wumpus
Just a reality check:

-At 1.8ghz, which is the projected top speed of the initial 970, it performs like a 2.8ghz P4 on SPEC. Even if the wider memory bandwidth does some magic, we are looking at running at the equivilent of a non-HT 3.06ghz P4. Better hope they are cheap, Apple will need to use 2 in each machine to become competitive on performance. We will be up against 3.6ghz+ HT P4s running on 800mhz FSB, not to mention the Hammer brigade.
Actually, we will be up against Intel's Deerfield, which is Itanium 3 (Merced) for the desktop (much as 970 is Power4 for the desktop). On SPEC numbers I believe the 1.8MHz introductory speed of the 970 in theory will best the Itanium 2, or at least be right about the same; no word on the Itanium 3 or Deerfield. Note, of course, that Deerfield will have lower SPEC numbers than it's heavy-iron big brothers, just as the 970 is a bit weaker than the Power4 at that clock rate would/will be.

AMD's story is about the same: Opteron ("Sledgehammer") is set to best the 970's SPEC numbers by a decent amount, but the same may not be true for its "little cousin", the desktop-aimed Clawhammer chip.

In the 32-bit world, we will be placing ~2GHz G4+'s against 3.2GHz P5s (note that P5 is to be debuting later in the year at 3.2GHz, albeit more efficient per cycle than the P4).

While one may compare the SPEC numbers between 32-bit and 64-bit processors, there is a reason why servers pay for the lower-performing 64-bit processors, and why processors like Itanium cost way more than P4s and Xeons. 64-bit processors, obviously, have the definite advantage that they can run 64-bit code along with the 32-bit SPEC calculations. The key on the high end is that Apple capitalizes on this ability with 64-bit iApps et al that "sing" compared to their 32-bit cousins.


Quote:

-ApplePI may have been the thing that helped to kill the 'G5' according to the reliable Architosh. It looks like a BIU to enable PPCs to run on HyperTransport, nForce-like mobos. If Apple did not need it, they would not have joined the consortium. It may enable Apple to rely more on partners like nVidia for mobos...Maybe Apple should have tried harder to get more out of Moto, even just real DDR support for the aged, inadequate G4.
Please stop this "fake DDR" nonsense. The PowerMac DDR is largely crippled by an undersized FSB to the CPU, but that does not make it "fake". Just not as effective as it should be.

Also note that RapidIO is Moto's entry into the "better FSB" world. Too little, too late, perhaps, but Apple is getting something from Moto too. Apple has choices, which as we all know is what it likes.

Quote:

-Many firms in Apple's target markets will want to upgrade and will not want what Ars Technica rightly called the 'overpriced embarassment' that is the current 'Pro' lineup. They will not be excited about 1.4ghz duals with fake DDR. They will buy PCs and not go back.
Quite true. The only hope for the next batch of pro(sumers) on the fence is if Moto can get a better FSB technology out the door with their 7457 chips. I'm no sure what the FSB is in these, but there are rumored to be both FSB and cache improvements.

To be absolutely clear: the bottlenecks we can see right now are in the System Controler-to-CPU bus, and in the L2 cache (which just exacerbates the deficient bus problem). This is what keeps the latest DDR machines from knocking your socks off, and this is also what keeps dual PPC machines from really shining (because both CPUs share that deficient bus). Given appropriate breakthroughs here, Apple's back in the game.

No FSB/cache breakthroughs, however, and fence sitters will be hoping off to Intel-land in droves.
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