There's no conflict
Using MHz as an indicator of raw speed is still a flawed argument, but the clock rate does still have a significant influence on overall performance. The reason you're concerned is that you have made up a whole new myth. We can call this the "pipeline premise." The pipeline premise suggests that shorter pipelines are always better.
Of course, it's easy to see that this isn't the case. Superscalar (pipelining) architecture was one of the major advancements that made our modern, zippy CPUs possible. There is no miracle of technology that would ever make it possible to clock an i386 or a 68040 up to gigahertz levels.
A canonical CPU has four stages: fetch, decode, execute and store. With no pipelining, only one instruction is in the queue at a time. With a pipelining architecture, when the first instruction moves onto the "decode" stage, the next instruction is queued up right away. In the best case, every stage of the instruction queue has an instruction to work on at every clock cycle. The difference in performance is the same as the difference between just hitting a home run and hitting a home run with bases loaded.
There's a minor (but tolerable) problem with this approach: It's not always possible to tell which instruction is the "next" instruction. If the first instruction is a conditional operation, there are two candidates for "next," and you can't know for sure until the first instruction has gone through the "execute" stage. The way this is handled is that the CPU and the software compiler cooperate to make a fair guess which instruction will be next. When you see the term "branch prediction," this is what is meant. Hopefully they pick right and the pipeline keeps chugging away. If they choose wrong, however, then all the work that has been done in the queue behind the first instruction is useless and must be discarded -- the entire pipeline must be flushed. Every time this happens, you've got to refill the pipeline before you start getting results again, and that takes a lot of time. The performance gain from good guesses, however, more than offsets the penalty for guessing wrong, and you're still doing WAY better than older processors that only worked on one instruction at a time (which, in superscalar terms, is like failing every branch prediction you make).
Another problem you run into is that your pipeline is only as fast as its slowest stage. In the four-stage processor described above, this is usually the execute stage. If your instruction takes eight clocks to execute, then everything behind it is going to sit idle for eight clocks, even if they all finished in one. The way we combat this problem is to break down the monolithic stages into much simpler substages that take as little time as possible. If your eight-clock execute stage can be broken into eight separate single-clock stages, then the following instructions will never have to wait. Having simpler stages allows you to pulse the clock more frequently because the simpler operations may be performed faster.
The big drawback here is that the longer your pipeline is, the bigger the performance hit you suffer when you have to flush it. Every time a 20-stage Intel chip misses a branch prediction it takes 20 cycles before the chip starts producing results again, because it has to refill the pipe.
So here's a very rough and dirty comparison: The current G4 has 7 stages. With a full pipe, instructions are completed on each cycle. If the pipe is flushed, it will take seven cycles before you see more instructions completed. If pipelining were turned off completely, the effective speed of a 700MHz chip would be 100MHz. That's the absolute worst case.
Now consider a G5 with a ten stage pipeline. At 1GHz (1000MHz), the worst case (no pipelining) would result in... 100MHz. To recap, a 1GHz 10-stage chip has similar worst-case performance to a 700MHz 7-stage chip. It's worth noting that the 1GHz will still have better average performance than the 700.
See, it's all a balancing act. MHz alone cannot determine a processor's performance. Nor can the length of the pipeline. In fact, the combination of the two is still dependent on the efficiency of the branch prediction, which is a much too complicated topic for either Motorola or Intel's marketing literature.
But note that all of the proposed G5 speeds are comfortably above 1GHz. Definitely a fair trade. That 1.6 is gonna rock.
