Difference between number of transistors of Merom VS Penryn.

Discussion in 'MacBook Pro' started by lauph, Mar 1, 2008.

  1. macrumors regular

    Joined:
    Jun 29, 2007
    Location:
    30 mins from Cupertino
    #1
    I read somewhere that Merom has 293million transistors, while Penryn has 410million transistors.

    So by transistor count alone Penryn has 40% more processing power than Merom. Adding to the 100MHz bump from 2.4 to 2.5, and the 3MB more L2 cahce, shouldn't the speed difference be way more than what the current reviews say?
     
  2. macrumors newbie

    Joined:
    Feb 4, 2008
    Location:
    West Des Moines, IA
    #2
    The L2 cache increase makes up a lot of that increased transistor count. Additional enhancements to the chip architecture make up the rest. More processing power with less heat, definitely a winner!

    Link
     
  3. macrumors regular

    Joined:
    Mar 1, 2008
    Location:
    USA
    #3
    The speed of the CPU has very little to do with the number of transistors. It depends on what those transistors are used for.

    OK, let's break this down (someone please tell me if my calculations are wrong):
    Typical SRAM cache uses six transistors per bit. There are eight bits per byte. Merom has 4MB cache, and Penryn has 6MB: an increase of 2MB or 2097152 Bytes.

    2097152 Bytes * 8 bits/byte * 6 transistors per bit = 100663296 or about 100 million transistors.

    So, if Penryn has 117 million more transistors than Merom, the vast majority of that difference is in the L2 cache. The reason why there is only a slight increase in performance is because the design of the CPU core is nearly the same. The new SSE4 instructions will significantly help only those programs that are written for them.
     
  4. thread starter macrumors regular

    Joined:
    Jun 29, 2007
    Location:
    30 mins from Cupertino
    #4
    So the 100million more transistors are just to accommodate the 50% increase in L2?

    And so the performance gain is just due to the increase in L2 cache?
     

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