# The Low Down on Processors--Where's the Physics?

Discussion in 'Macintosh Computers' started by themadchemist, Jun 16, 2004.

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#1
Some of you guys are very knowledgeable on this front...When we were waiting for the 90nm chip, all I could hear was that the smaller process would mean less power consumption, meaning higher frequencies, meaning a happier world. Someone once told me that increasing the surface area of the processor has a similar effect, as well.

I'd like more detail on this. Let's start from the basics. What, physically, is the process? Is it the width of the transistor or what? What effect does the size of the process have on performance and on power consumption?

What are the physical laws in play here? I realize that at this size it's Newtonian. Could we have a few equations, maybe some diagrams, and an explanation of what's going on here from the standpoint of physics?

I think that this would be of enormous interest not only to me, but to other inquisitive individuals who would appreciate a closer look at the things that we're always rattling off about.

2. ### varmit macrumors 68000

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Aug 5, 2003
#2
Ok, here is it in a good way to figure it out. Going from NY city to San Fransisco. Long distance, mainland USA is big, takes a long time to make it. Now make the USA smaller, say like Hawaii, like making a chip smaller, takes less time at the same speed thus the processor can process information in less time or you can drive from NY to San Fran in less time. Or, you don't need to go as fast to get there in the same amount of time as before, as in less Ghz, and later you ran go faster making the trip even shorter, making the process faster. Shorter distance, less speed help reduce heat because there is less wire, aka roadway to heat up your oil.

That is a short sweet way of thing about it.

A process is start to finish or an instruction that is given to a processor. One set of calculations, not mulitiple sets that then get made into a picture or something, but a single pixel.

Little bit of physics, some chemistry i think. Basic electricity though wire physics. More resistance, more heat. Useless wire, less heat produced.

3. ### PlaceofDis macrumors Core

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#3

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#4
Your analogy is wrong. A 130nm 2Ghz G5 will perform exactly the same as a 90nm 2 Ghz G5. Its not any quicker just because it is smaller.

5. ### belair macrumors 6502

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#5
The 90nm aint faster than the 130nm but it will use less energy an create less heat. That way with the 90nm you can travel from Ny to SF using less patrol. Good enough for me, but then again I live in Europe and patrol is really expensive here compared to the states.

6. ### floatingspirit macrumors 6502

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#6
I think we should check this poster. He could be an intelligent life form from another planet with questionable intentions! He may be trying to steal our precious technological secrets!

7. ### Mac_Max macrumors 6502

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#7
A 90nm process requires less power than a 130nm one because there are less electors that need to flow because of decreased resistance. This has a side effect of creating less heat. Going from a CMOS based process to a SOI process also does this. On the current 90nm process there have been probles with electors leaking away from the cicuits they are supposed to be in & cause problems with heat and with heat comes instability & possibly a mealted CPU if its not kept in check.

8. ### ewinemiller macrumors 6502

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#8
You could extend the analogy a little and make it work. It's more like your car (the electron) has to move from city to city on a schedule (the clock signal). You shrink the map, the car gets there faster with less energy spent, but if you don't shorten the schedule, all you save is energy. The key is now instead of saying you've got 6 hours to travel to each city, since the distance is shorter, we're only going to give you 4 hours, i.e. we're upping the clock speed.

Some of the problems that everyone are having related to moving to 90nm is that while the map shrunk, the electrons didn't. So to beat the metaphor a little more, now you have narrower roads and the medians between them are smaller. You've got congestion (heat), and people are driving across the medians (leakage).

9. ### osprey76 macrumors 6502

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#9
Along with induction in adjacent wires. Current through a wire generates a magnetic field, magnetic fields can induce current. So, there is the possibiliity along two parallel wires for one to influence the other. Not a desired effect in a microprocessor.

There are a few of other benefits that come to mind. Shrinking the die for reduced heat is important, too, because there is only so much heat that the silicon chip can transfer. By generating less heat at a given clock speed, you now can ramp that speed up but stay within your maximum heat transfer rate. Make a cooling solution outside of the chip is fairly straightforward (doing it quietly is a whole other ball of wax), but getting the heat out of the chip itself is the crucial factor.

Along with the heat issue, you still have to stick to the laws of physics. For the whole chip to be synced, the physically longest path must be able to be travelled in one clock cycle. Since electrons move at roughly the speed of light, in a 1 Hz chip, you have 3x10^8 meter maximum path length. At 3 Hz, you get 1x10^8 meters. At 2.5 GHz, you have a maximum path length of 0.12 millimeters. The actual speed of an electron in a circuit isn't quite the speed of light, so you can fudge it down a bit to say 100 micrometers. So, to keep bumping your clock speed up, you have to reduce the size of the chip. Clock speed doesn't define the power of chip, but it certainly does make an increase in two chips of the same design.

This principle is a primary reason that motherboards have been relatively slow to ramp up in speed. The component (PCI cards, etc.) just need physical room and that makes for a larger board and limits the speeds. To work around this on things like memory, Apple et al., use dedicated buses for just RAM outside of the main bus. Since the scope and physical size of the bus is small, they can ramp up the speed.

Also, IBM, et al., use 12" or more platters of silicon that go through the chip making process. If you reduce the footprint of the chip, assuming a given yield (percentage of processors that actually work off of a given platter), you get more processors. Once manufacturing issues are worked out, you get more chips on a platter for roughly the same amount of effort. That means each chip is cheaper to make and, with time and the possible volumes that the next generation video game consoles will generate, the chips will be cheaper to buy. Whether Apple passes the savings along is a valid question, though.

For more information check out Ars Technica. That's where I learned some of what I've written here. They have some excellent comparisons between various processors (Ex. Pentium4 and G5) that sheds some light on why one does some things better than the other and vice versa.

10. ### AtiLaw macrumors newbie

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#10
This story might shed a little light over some problems with speed and the advantages intel got from making their chips 90nm. I read it some time ago but your question reminded me of the story.

http://www.newscientist.com/news/news.jsp?id=ns99994493

Its not specifically directed at Mac, because it is about Intel's method of silicon straining, but it might help!

11. ### pjkelnhofer macrumors 6502a

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#11
This is an excellent point, and it brings up something even more important. There is a point at which you simply cannot make chips much smaller. An atom is about 0.5nm in "diameter" (I put diameter in quotes because it is hard to say that an atom really has a diamter at all). That means that that the current chips is on the order of 200 atoms thick.
With talk on the next generation chips being 65nm this is over a 25% reduction in thickness. About five years ago chips were 180nm thick. I don't see how chips can continue to shrink without problems such as induction becoming too severe.

12. ### AtiLaw macrumors newbie

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#12
Optical processors are in development, I think a few people have even started selling them commercially. Eventually quantum computing will be reality too. There is always another technology willing to take over when you reach the limits of the current one.

13. ### pjkelnhofer macrumors 6502a

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#13
Optical processors will not to be smaller than silicon because there will be less heat and photon travel faster than electrons. The chips will still have to be able to have some sort of fiber optic cable which once again could never be smaller than one atom in diameter. Not to mention you need something to generate the light (a laser is usually used).
We are quickly reaching the physical limitations of silicon based chips and nothing I have read about optical processors leads me to believe that they are knocking on the door ready to take over.
I am not sure that I believe that quantum computing will ever exist (unless you can disprove the Heisenberg Uncertainty Principle.)

14. ### AtiLaw macrumors newbie

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#14
Im not sure how they do it, but from some of the reports I read I get the impression people are already using optical processors.
http://www.lenslet.com/docs/EnLight256_White_Paper.pdf
They sell an optical DSP apparently.

I'm not saying that these technologies are ready to take over right now, but by the time silicon has reached it limits im sure the big companys would have poured aload of money into research for the next big thing, the optical and quantum technologies are just ones I see alot of hype about.

15. ### Catfish_Man macrumors 68030

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#15
It looks like a lot of the issues (induction, wire length, etc...) have been covered, but I did want to mention one interesting one. The original poster's assumption that we're working with essentially Newtonian physics isn't quite correct. If I remember correctly a slightly significant (although single digit) percentage of the .09 micron Pentium 4's leakage current comes from quantum effects, specifically electrons tunneling through the gate of transistors that are supposed to be off. This effect is only going to get worse as the gate length decreases.

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Jun 24, 2003
#16
I think we're almost at that point, or will be in a few years. There's a Register article about it saying how the 130nm-to-90nm process didn't exactly reduce heat dissipation and the upcoming 90nm-to-65nm process is going to be worse.

17. ### Rend It macrumors 6502

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#17
Now for something completely different

Ugh. I know TheMadChemist from other forums to be quite the intelligent one. So, I'll try and give him what he originally asked for: Physics. First, there are two main things that cause heat in a semiconductor as complicated as a processor. The first is common series resistance, along the lines of Ohm's law: V=I*R. Now, even with Cu interconnects, there will still be some measurable resistance between points in a chip for 2 reasons: 1) The interconnects are VERY narrow and flat (small cross section). The relationship between resistance and wire dimensions is R=(rho*L)/A. The greek letter rho is the resistivity of the material in units of [Ohm*m]. L and A are the length and cross-sectional area, respectively.

The 2nd reason for a series resistance is due to the skin effect. At high enough frequencies (like several GHz), current does not travel in the bulk of a wire, but is rather confined to travel on the surface. So, the actual cross-sectional area is even less. The measure of this effect is given by the skin depth (lambda), which is the characteristic length the current penetrates into the wire. Typically, the current density decays into the wire as exp(-x/lambda), where x is the distance from the outer surface of the wire inward.

Also, the current in the wire does not travel close to the speed of light, it's actually quite slow. What does travel close to c is the signal, or the change in the electric potential across the wire. There's actually not much current flow at all in modern processors. Metal-oxide semiconductors don't need it; they respond just fine to rapid changes in potential. Now, anyone familiar with elementary circuit theory should now be realizing that if the change in potential is what's important, then capacitive effects must also be critical.

Another problem: Parasitic capacitance. If you have two circuit traces very close to one another, they will have some capacitance between them. The capacitance per length of two parallel wires goes as roughly log(1/d), where d is the separation length. So, the closer the wires, the bigger the capacitance. Also, the shunting effect of the capacitance between wires becomes worse at higher frequencies. So, for close wires with high frequencies, we end up with an attenuation in signal along the length of the wire (this is exactly the same problem as dealing with transmission lines).

But, the above paragraph is not a cause of heat, but rather shows why you want short wires between transistors, but long distances between individual wires. The 2nd cause of heat aside from series resistance is also due to capacitance between wires, but has to do with the imaginary (as in square root of -1) part of the complex capacitance, not the real part. FYI, you can write the complex capacitance as C*=C'+iC", where C' is the real part, and C'' is the imaginary part. This is caused by using lossy insulating materials (dielectrics) between the wires, such as Si. Now, SiO2 is a wonderfully low-loss insulator, and is being used by IBM to replace the conventional silicon, thereby giving them fairly good results (much better than Intel with strained silicon) in regards to heat dissipation. Conventionally, the measure of an insulator's lossiness is given by its dissipation factor, also called loss tangent. This is the ratio of the imaginary part of the complex capacitance to the real part: tan(delta)=C''/C'.

Hope that clears things up.

One more thing: quantum computing has little or nothing to do with Heisenberg's uncertainty principle. The practical success of it will depend greatly on a little something called DECOHERENCE. For an introduction, check out John Polkinghorne's little book.

18. ### AtiLaw macrumors newbie

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#19
Analogy is still wrong, the causality is wrong. Going to a smaller process helps you get the Mhz up which improves your performance. The die shrink in itself doesn't make anything faster.

Upping the clock speed is equivalent to driving faster.

20. ### Rend It macrumors 6502

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#20
Just clarification

I hinted at this in my previous post, but just to clarify, the current required to see the magnetic induction you're speaking of would easily fry the delicate metal-oxide transistors. It's true that two parallel wires will influence each other, but it is a completely capacitive effect in microprocessors. One of the major reasons the entire digital industry moved away from bipolar technology back in the 70's was to reduce heat from current flow in those devices. Even the quiescent current (current when no signal is transmitted) was large in that technology. That's why field-effect transistors are so ubiquitous in the logic industry: they modulate the signal based on electric potential at the gate, as opposed to modulating the signal with a base current in BJTs. Now, of course for RF power amplifiers one usually sees BJTs with fancy materials like SiC or GaAs, but that's another story.

Again, the drift current in semiconductors (or even metals for that matter) is enormously slow (think turtles). This problem is usually worked out in freshman physics texts, so I won't do it here. But, it doesn't matter because you don't care how fast electrons are flowing, you simply care about how fast you can change the electric potential. Just as with multimode fibers, you get dispersion of light pulses, you will also see signal dispersion in a metal for electrical signals. Dispersion is when a material allows some frequencies to propagate faster than others, like the index of refraction for light. It's what turns square pulses into rounded, gaussian-shaped ones. Dispersion is typically the limiting factor when you're worried about how fast a signal can propagate down a wire (or any transmission line).

As for the rest of the comments, I'm afraid my physics knowledge stopped when you mentioned the phrase, "manufacturing issues."

21. ### thatwendigo macrumors 6502a

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#21
Nice to see some other people bringing not only physics, but physics that's beyond what I've been taught or taught myself.

That being said, I think that we've left out an important part of the die-shrink move that isn't really being talked about all that much below the level of technical whitepapers: surface area. I recently looked up the die size for the 130nm and 90nm 970, 970FX, Pentium 4 Northwoods, and Pentium 4 Prescott chips so that I could do a little math to check something I'd been wondering about.

Look here for that, since the moderators don't like seeing direct resposts

The point of the matter is that, as you increase clock on a smaller process, you begin to edge the heat back up to its previous levels but don't have nearly the same amount of space to dissipate it from. The Pentium 4 didn't suffer this effect as much because it only shrank some 23mm^2 on the redesign (145mm^2 to 122mm^2), but the 970 to 970fx move reduced the die by roughly half, from 118mm^2 to 60mm^2. We don't know yet just what the 970fx will be running, wattage-wise, at 2.5ghz, but an assumption that it's around the heat of the original 130nm 2.0ghz 970 allows us to draw a conclusion.

130nm 970 2.0ghz (118mm^2)
--0.43watts per mm^2 (typical wattage of 51)
--0.86watts per mm^2 (maximum wattage of 102 - I'm assuming this figure from the typical)

90nm 970fx 2.0ghz (60mm^2)
--0.41watts per mm^2 (typical wattage of 24.5)
--0.81watts per mm^2 (maximum wattage of 49)

90nm 970fx 2.5ghz (60mm^2)
--0.85watts per mm^2 (typical wattage of 51)
--1.7watts per mm^2 (maximum wattage of 102)

The dissipation needs of the 2.5ghz part could easily be the same as the maximum of the previous chip, when running at typical usage and roughly double the maximum. As such, the LCS module could entirely be an issue of quiet operation and proof of concept, a way to keep from running a "windtunnel" product as they did with the MDD G4 towers. The problem is evacuating the heat from a smaller surface, without much in the way of a lessening of the overall temperature and waste heat from the die shrink once the clock has been scaled.

22. ### savar macrumors 68000

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#22
For those of you who are not quantum theorists. (Or at least haven't read "The Elegant Universe")..here is my naive explanation of the above:

"Quantum tunneling" refers to a phenomenon where a solid particle moves through another solid particle. Its like throwing a baseball at a brick wall and instead of bouncing back it flies straight through. This is because at the quantum level, movements can be described only by probability statements..statements which assign a likelihood of any particular path being chosen. Well some of those possible paths go straight through other "solid" objects.

In fact, even larger objects that we can see have some nonzero probability of tunneling. The reason why you've never seen a baseball fly through a wall, however, is (if I understand correctly) the baseball is composed of numerous particles each with a very small probability of tunneling, and when all those probabilities are taken at once, the probability is so small that not even in the entire history of the universe has something the size of a baseball tunnelled. (Its like flipping a coin. Getting heads once is .5 probability. But getting it twice is .5 squared, or .25. What about getting heads a million times in a row? That probability is infintesimally small.)

So when the above poster is talking about electrons tunneling, he means that the transistors' gates have few enough particles in them that the probability of an electron tunneling reaches the point where it actually happens a significant amount of time.

I'm not a physicist, so anybody who knows more please correct. This is just what I've learned from Dan Brown's book.

23. ### johnnyjibbs macrumors 68030

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#23
I think his anology is right, because shrinking the map enables you to get there quicker while travelling at the same speed because the distance is shorter. Because this then means the car/electron, whatever, then has some time to spare due to the shorter distance travelled, this enables them to increase the speed (i.e. reduce the allocated time between cities). The speed of the car doesn't change with increased clock speed (i.e. electrons always travel at appraoching the speed of light, regardless of clock speed).

Also, to the guy who said at 2.5GHz, the maximum path length is 0.12 mm, this is 120 microns or 120000 nm. Wouldn't this allow the clockspeed to go to several thousand GHz for the maximum length to get to 90nm, which is where we are now at?

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#24
Well, considering a 2Ghz 90nm G5 performs exactly the same as a 2Ghz 130nm G5 I find it difficult to see how you can draw that conclusion.

25. ### johnnyjibbs macrumors 68030

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#25
Yes, they perform the same but the 90nm version uses less energy and heat, allowing extra room for increasing the clock speed and therefore "reducing the journey time"