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Discussion in 'Community' started by arn, Feb 18, 2004.
Human translation please.
ISSCC: Power-consumtion cuts for 90nm
The 64-bit processor type PowerPC 970 (Power4-core with SIMD-extension and bigger cache) is currently produced by IBM using a 130nm-process. In preperation for the building with 90nm, the developers now introduced new techniques for frequency and electrical power. Already before the start of the ISSCC it became known that IBM is going to work with strained silicon in the 90nm-process, additionally to copper and silicon on inllustrator (SOI).
Under certain sircumstances, a process called PowerTune will cut down the speed to half or even a forth of the processors maximum speed. On both of these lower levels, the electrical power used can be reduced, resulting in a smaller power consumption. Additionally, the chip is able to go to a nap-mode in every frequency-power-combination. The last step, the sleep-mode, eventually reduces power even more, while the chip operates at 1/64 of its maximum speed. The speed is still high and the needed impuls small enough to prevent negative history-effects after waking up from sleep, an IBM-developer stated at the ISSCC. Inspite of the new name, the PowerTune technique sounds familiar, since Intel (Speedstep) and AMD (PowerNow) tried similar things with their chips.
While IBM reduces the chip size almost by the factor 2 (from 118 (130nm) to 62 (90nm) squaremillimeters), the usual power consumption is said to drop from 66 Watt at 2GHz to 50 Watt at 2,5GHz. With active scaling of speed (to 625MHz) and electrical power (1V), the PowerPC only consumes 12 Watt. Apple wants to begin shipping Xserves using the PowerPC 970FX as early as this month. Sony and Intel showed their approaches to saving power at this ISSCC as well. Sun is trying to achieve similar results as IBM with their dual-core-architecture for the ultrasparc-chip.
I hope this helps and I got all the technical stuff right, but I think that must be about it. Nothing special I guess, just some more input on how PowerTune works... sleep mode just for the processor sounds good
(Click the fish for the linkie.)
Always good for a laugh
Just to clarify the difference between nap mode and deep sleep mode:
IBM produces his 64-bit-processors PowerPC 970 (Power4-Core with SIMD extension and large cache) in a 130nm process at this time. In preparation for the 90nm process the developer team has introduced new control methods for frequency and voltage. Already known before ISSCC was IBM using strained silicon besides copper and silicon on insulator in the 90nm process.
Under certain conditions a process called PowerTune will decrease the clock rate to half or even a quarter of the maximum frequency. On both levels the voltage can be decreased to decrease power usage. Furthermore, the chip can go to a nap mode in each clock rate-voltage-combination (?). Then, the deep sleep mode decreases power usage even further, while the chip works with the 64th part of ist maximum frequency. Still, the clock rate remains high enough but the required energy low enough to avoid the neagtive history-effects when waking up from deep sleep, an IBM developer said at ISSCC. Despite the new name the PowerTune technique sounds familiar, as Intel (Speedstep) and AMD (PowerNow) have done something similar with their chips.
While IBM nearly halves the chip area from 118 to 62 squaremillimeters, the average power usage is said to decrease from 66 Watt at 2GHz to 50 Watt at 2.5GHZ. With activated scaling of frequency (to 625MHz) and voltage (1V) the PowerPC 970 will only use 12 Watt. Apple wants to deliver systems equipped with the PowerPC 970FX namely Xserves this month. Sony and Intel also show their power saving efforts at the ISSCC. Sun also emulates IBMs Dual-Core-architecture for the Ultrasparc chip.
Oops, I overread that... sorry... yes, there is a difference, I'll correct my translation
And I recommend your translation as it's far better than mine.
Best thing to do is to read both, then you'll all know best what the article is trying to say...