hmm how is it possible

[phantommaul]

133MHz system bus supporting over 1GB/s data throughput

i have witnessed everyone complaining about the 133 system bus ( the general idea for them are out of date)

but this quote is taken from the specifications of XServe and they say it has the capacity of 1GB/s

and now i ask u (because i really dont know)
how could this happen (teach me the principal of system bus)
because i dont see any slow transfer times here

 

[macstudent]

I thought it was 266mhz ddr ram, not 133

 

[sturm375]

System Bus

I don't pretend to know everything about this issue, but I think I can supply you with some information.

There are several different areas that comprise the System Bus. I think what they are talking about here is the bus from the processor(s) and the RAM. Since we are talking about DDR RAM here, the data path into and out of the RAM is 128-bits wide. Actually that is 64-bit one way and 64-bit the other way. So Idealy we are talking about a theoretical maximum data throughput on this specific bus of 8.5 Gb/s. To get that you take the number of cycles in each second (133,000,000=133 MHz) and multiply that by 64 (the number of bit streams. Now remember I said 8.5 Gb/s, not GB/s, Gb=Giga-bit, GB=Giga-Byte. 1 Byte=8 bits, so you are about 1 GB/s real world transfer.

Now I left out a few things to get to the number Apple posted. If we were really talking about a completely 128-bit bus to DDR memory, the number would be much greater.

DDR=1 Write+1 Read each clock cycle (which is where they get the DDR 266 {2x133=266})

Now we are looking at a theoritical max of 17 Gb/s or 2.1 GB/s. However this is not a perfect system as the processor(s) are still 32-bit.

That is the main bus, and the one I think they are referencing in the ad. But don't forget there is much more going on in a computer than just processor to RAM. You can't forget about the PCI bus, IO bus (keyboard, mouse, USB, serial, ethernet, video), and HD bus.

Right now the slowest part of your computer is the Disk. The fastest IDE is now at 133 MB/s burst speed. And that is only one direction. These machines (Xserve) use ATA 100 Hard drives, which have a burst speed of 100 MB/s, and since they are IDE, you can only access one disk at a time. That is where SCSI excels. With an array of SCSI disks, you can have data going in and comming out of all hard drives at the same time. I think their data transfer rate is slightly faster as well.

I hope this helps

 

[Catfish_Man]

Re: hmm how is it possible

Originally posted by phantommaul


i have witnessed everyone complaining about the 133 system bus ( the general idea for them are out of date)

but this quote is taken from the specifications of XServe and they say it has the capacity of 1GB/s

and now i ask u (because i really dont know)
how could this happen (teach me the principal of system bus)
because i dont see any slow transfer times here

Well, to give you an idea of the competition, an AthlonXP's bus does 2.1Gb/sec, A new P4's does 4.2, a GeForce4 Ti does 10.2, and a Matrox Parhelia does 20. 133MHz Single Data Rate is approximately enough to completely handle a single 533MHz G4+, without anything else using the bus. So the ideal bus for the current dual 1GHz G4s would be something that runs at the same speed as the Pentium 4's bus (the P4 actually has a dual channel double data rate 133MHz bus, for 4x the effective bandwidth). A 500MHz RapidIO bus (speculated for the G5) would fit the job quite nicely.

 

[wrylachlan]

Re: Re: hmm how is it possible

Originally posted by Catfish_Man


Well, to give you an idea of the competition, an AthlonXP's bus does 2.1Gb/sec, A new P4's does 4.2, a GeForce4 Ti does 10.2, and a Matrox Parhelia does 20. 133MHz Single Data Rate is approximately enough to completely handle a single 533MHz G4+, without anything else using the bus. So the ideal bus for the current dual 1GHz G4s would be something that runs at the same speed as the Pentium 4's bus (the P4 actually has a dual channel double data rate 133MHz bus, for 4x the effective bandwidth). A 500MHz RapidIO bus (speculated for the G5) would fit the job quite nicely.

This is all true, but because a 533 G4 can max out the bus doesn't mean it will all the time or even most of the time. Nor does it mean that if a 533 can max out the bus that a DP 1Ghz is bottlenecked to 1/4 it's potential by the bus. The fact is that in a well designed system, the vast majority of the info the chip is going to need to keep itself busy is available in cache.

In fact, the G4 is much more efficient at using its cache than x86 chips, which is why apple has waited so long to go to DDR. If Apple was using AMD or Intel chips they would have been forced to go to DDR long ago.

Please note that I am not saying I don't want a faster bus. I do. But I am under no delusion that doubling the bus speed will double the speed of all my applications.

Also, for a frame of reference, a DV stream does not fill up the 400MBps firewire, so a slightly more than 1GBps bus could essentially pass three full DV streams across it at once. If the chip could do the math that fast, the bus would provide it plenty of bandwith to do green-screening in realtime. That is already a lot of power.

I think Apple is taking its time because it is being realistic about the cost/benefit ratio. Not that I can't want the moon. I do want the moon and my RapidIO bus (though Hypertransport would be better IMHO).