HP slips Athlon64 specs, how compare to g5?

Discussion in 'Macintosh Computers' started by crayzaysean, Jun 19, 2003.

  1. crayzaysean macrumors newbie

    Jul 12, 2002
    ZDNet Article

    AMD are naming their new athlon64 which runs at 1.8ghz the 3100+. Since we all know their naming scheme is to give the impression that it runs comparable to a p4 with that number of megahertz, then they believe that the athlon64 is comparable to a 3.1ghz p4 in some cases, right?

    My question is then how does the 970 stack up to the athlon64? Would a 1.8ghz 970 run comparably to a 3ghz p4 if the athlon supposedly does? IF SO, then we could feasibly get just single proc. models, right? And if they were duals then..."my comp is like, WOAH!"
  2. goglamosh macrumors member

    Jul 7, 2002
    at least apple's G5 offering will match up Mhz for Mhz with the Athlon64, regardless of real performance, in the 64 bit market.
  3. G3-Pwnz-G4 macrumors regular

    Jun 5, 2003
    lol, which proves that mhz isn't everything, as the window's user blatantly denies....such ignorance is funny.
  4. hvfsl macrumors 68000


    Jul 9, 2001
    London, UK
    The P4 has a high Mhz, but the PPC970 and AMD K8 process more instruction per clock. Also Intels Itanium is blarely over 1Ghz and it is aimed at heavy weight servers. The problem with the G4 was that the parts that connected the chip to the rest of the componants were too slow and causing bottlenecks.

    I remember seeing some performance benchmarks of a 3Ghz P4, a 1.8Ghz PPC970 and a 1.8Ghz K8. The PPC970 was slightly faster than the K8 which was faster than the P4. However a remember that in 3D graphics the PPC970 was about 30% faster than the P4.

    However Intel is set to release a new version of the P4 that will be even faster and that is what the PPC970 has to measure up to, not any current chips.

    Edit: The K8 is another name for the Athlon64.
  5. PowerBook User macrumors regular

    May 29, 2003
    If that benchmark is even close to accurate, that would mean quite an improvement in Power Mac speed! :) At least there will be a noticable inprovement.
  6. hvfsl macrumors 68000


    Jul 9, 2001
    London, UK
    The testing was done on SPEC benchmarking programs. If you search google you might still find it somewhere.
  7. MorganX macrumors 6502a


    Jan 20, 2003
    While this is true it is the large caches that keep lower MHz CPUs in the game. Give them all the same cache and more instructions per cycle or not, the CPU with a constant 2:1 clock ration will probably win in the real world.
  8. Cubeboy macrumors regular

    Mar 25, 2003
    Bridgewater NJ
    Depends on the processors, assuming other conditions are the same, a CPU that issues 1 instruction per clockcycle ands runs through 1000 clockcycles every second (1 GHz) will perform the same as a CPU that issues 2 instructions per clockcycle and runs through 500 clockcycles every second. Of course, thats assuming all the instructions are at a given length. Which depending on the architecture of your CPU, can be very difficult to determine.

    I will go into more detail with this below:

    The Pentium 4 should be able to issue and retire up to 3 instructions but since your typical x86 instruction is 1.5 micro-ops in length, it can really issue on average issue maybe 2 instructions, more with shorter instructions, less with longer instructions. The number of instructions our Pentium 4 (and any other CISC chip for that matter) is capable of issuing thus depends on the length of each instruction in the pipeline.

    On the other hand, RISC instructions are all the same length (thus allowing for the likes of parallel pipelining, streamlined instruction sets, etc). Because of that, the number of instructions that can be issued remains the same no matter what.

    So to put it into context, it's fairly easy to determine the IPC of RISC chips since all the instructions are equal, it's downright impossible to determine the absolute IPC of a CISC chip, since it varies depending on the instructions used. All you can really do is determine the average length of a instruction in the CPU's instruction set and assume both long and short instructions will be in the pipeline at a given time. It's still a fairly accurate method in the end but certainly not without flaws.

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