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IBM (and others) join HT Consortium

Ambrose Chapel

macrumors 65816
Jul 24, 2002
1,141
3
Massachusetts
so does this mean we should expect this tech to appear in the PPC 980? could IBM have been working on it before joining the consortium, or would all work have to commence afterwards?
 

dstorey

macrumors 6502a
Dec 14, 2002
527
0
As the 970's don't support Hyper Transport, and Apple had to use a bridge chip to connect it to their hypertransport Mobo, doesn't anyone know if the system takes a performance hit due to this?
 

tazznb

macrumors regular
Jul 22, 2002
141
0
New Jersey
HyperTransport Consortium....

I used to be on the HyperTransport Consortium, but had to relieve myself of that post; I ate too many Prangles, and it started to disagree with my bowels.

Not all chips are good for you.:(
 

Cubeboy

macrumors regular
Mar 25, 2003
249
0
Bridgewater NJ
Originally posted by dstorey
As the 970's don't support Hyper Transport, and Apple had to use a bridge chip to connect it to their hypertransport Mobo, doesn't anyone know if the system takes a performance hit due to this?

Doubtful, the G5's bus is very similar to a hypertranport bus, even if there is a performance hit, it would be minimal. Are you referring to the hypertransport interconnects used for I/O? I don't recall any other HT features on the G5 Powermac.
 

Powerbook G5

macrumors 68040
Jun 23, 2003
3,974
0
St Augustine, FL
It seems like the G5 has a quick enough system as a whole to offset any speed penelty, but truthfully, it can only be that much faster having it integrated since having an external bridge will have to slow things down by its very nature.
 

NuVector

macrumors newbie
Nov 29, 2002
8
0
Don't be silly.

Originally posted by dstorey
As the 970's don't support Hyper Transport, and Apple had to use a bridge chip to connect it to their hypertransport Mobo, doesn't anyone know if the system takes a performance hit due to this?
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.
 

cc bcc

macrumors 6502
Jul 3, 2001
470
0
nl
Re: Don't be silly.

Originally posted by NuVector
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.

Didn't IBM say that they will include an on die memory controller is the ppc980? I forgot where I read it.

edit: So no timetable was given for an integrated memory controller: link
Similarly there was a general exposition of memory latency issues
(which are of course directly related to SMT issues), and in response
to a question from the floor the advantages of integrated memory
controllers were warmly compared to Opteron, and again the
"roadmapish" statement made that IBM will provide such, but no time given.
 

dstorey

macrumors 6502a
Dec 14, 2002
527
0
Re: Don't be silly.

Originally posted by NuVector
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.

So if IBM re-engineer their powerpc family, as the article suggests they will be, then what advantages, if any, will it give? I guess the northbridge and southbridge will be able to conect via hyper transport than, as well as the rest, creating the hyper transport ring that i've heard mentioned...but i guess this will be no faster..maybe just easier to engineer and produce?
 

bcsimac

macrumors 6502
Nov 4, 2002
275
0
Bolivar, TN
A wise move if you ask me!

I think IBM joining is a good move and a wise one at that. I think it can only help the hypertransport technology grow and become standard and help Apple to continue to implement it in their systems.
 

Sun Baked

macrumors G5
May 19, 2002
14,859
57
Don't mix up supporting a technology with applying the technology to the CPU. ;)

From ARS Technica
Originally posted by Sun Baked:
IBM has said they would be supporting a wide range of technologies in their custom ASIC business.

They even list HT as one of the available Blue Logic Cores for the custome ASIC division.

http://www-3.ibm.com/chips/products/asics/products/cores/corelist.html

Would almost expect them to join the consortium...
 

Cubeboy

macrumors regular
Mar 25, 2003
249
0
Bridgewater NJ
Re: Re: Don't be silly.

Originally posted by dstorey
So if IBM re-engineer their powerpc family, as the article suggests they will be, then what advantages, if any, will it give? I guess the northbridge and southbridge will be able to conect via hyper transport than, as well as the rest, creating the hyper transport ring that i've heard mentioned...but i guess this will be no faster..maybe just easier to engineer and produce?

Lower latency (no data encoding), differential IO signalling (no clock overhead), coherency, scalable bandwidth, need I go on? There's going to be many performance advantages from using a hypertransport bus, especially among dual and multi-processor systems.

Plus it's cheap to implement, and compatible with existing PCI/PCI-X and legacy I/O technologies.

Hypertransport was developed in large part by AMD, IBM and Intel are both working on their own I/O protocols, specifically RapidIO (IBM) and PCI Express (Intel).
 
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