MWNY DDR RAM? Actual G4 does NOT support DDRam!!!

Discussion in 'Hardware Rumors' started by ricotta, Jun 27, 2002.

  1. ricotta macrumors newbie

    Jun 27, 2002
    Hello guys,

    just found the G4 MPC 7455 specs (800, 933, 1 GHz) at motorola homepage:

    "Max. 133 MHZ Bus" !!!

    This means, that the actual G4 chips dont have a native support for DDRam at higher Bus speed. The performance increase at MWNY will be a joke (max. 10%), cause there are NO new G4 processors on the way in the next months. Just take a closer look at Motorolas page...
  2. PCUser macrumors regular

    Mar 1, 2002
    266MHz DDR memory USES 133MHz bus. It uses a 133MHz bus and doubles the data across it.

    Besides... the Xserve already HAS DDR266. The G4 most certainly does support DDR.
  3. Beej macrumors 68020


    Jan 6, 2002
    Buffy's bedroom
    Beautifully summed up.

    There is no question that the G4 can use DDR. People that are hoping to see bumps up to 166 at MWNY are the crazy ones, not the ones expecting DDR with 133.
  4. amnesiac1984 macrumors 6502a

    Jun 9, 2002
    its okay ricotta we forgive you, we all make mistakes

    :p :p
  5. Megaquad macrumors 6502a

    Jul 12, 2001
  6. Macmaniac macrumors 68040


    X serve and DDR! I thought I heard that the DDR on the X Serve does not double the system bus! It is still listed as 133, not 266! Am I being stupid?
  7. ricotta thread starter macrumors newbie

    Jun 27, 2002

    kind of my fault - or my bad english.

    I just meant, if the new G4s stays at 133 MHZ the DDR just adds 10% of speed. Not more.

    (266MHz DDR memory uses 133MHz bus.)

    Maybe the actual DP G4 1 GHz with all its rebates is the better choice...
  8. drastik macrumors 6502a


    Apr 10, 2002
    I would think it does support DDR. Why waste money throwing more expensive RAM into a machine that can't use it. Apple's not about going for the name alone.
  9. Backtothemac macrumors 601


    Jan 3, 2002
    San Destin Florida
    Um, no. The processors will move to a 1.4GHZ in the high end with DDR, and will be a lot faster than the current staple of systems available. Not to mention, but it will hold far more memory than before. Yea, the Dual 1GHZ is sweet, but it won't hold a candle to the G4's next month.
  10. blakespot Administrator


    Jun 4, 2000
    Alexandria, VA
    The system bus is still 133. The data is read on the leading and trailing edge of the clock pulse, hence the DOUBLE data rate.

  11. Postal macrumors regular

    Jun 22, 2002
    Ottawa, ON, Canada
    As I understand it, the front-side bus on the Xserve is still 133 MHz (no DDR or anything), while the RAM is the DDR element (133 MHz x 2).

    That's not to say that there won't be a change come MWNY; it's possible that the system bus will also be doubled, so you'd have DDR all around the system. Presumably such a change would apply to both the PowerMac and Xserve (since the Xserve is supposed to be Apple's highest-end product).
  12. Backtothemac macrumors 601


    Jan 3, 2002
    San Destin Florida
    OMG! There is no such thing as a DDR bus. Bus is Bus. It is either 133 with SD Ram, or DDR. 200, 266, or in the PIV 100MHZ with a force multiplier with theoretical speed of 400 MHZ.

    Athlons us 200, or 266. DDR is for the memory only! It doubles the data rate. From 133 to 266MHZ. That is how it works.
  13. mischief macrumors 68030


    Aug 1, 2001
    Santa Cruz Ca

    Jeez guys.

    The xServe may very well be using a standard Apollo G4 because (if you dig into the spec) it uses "a custom ASIC" bus and RAM controller. Effecxtively Apple's cheating by using what I can only assume is an embedded-switch chip to offload DDR from the CPU.

    This approach leaves a ton of room for making the transition to a G5-based bus without major chip revisions to raise costs. Apple could just tweak the ASIC (hell, it may even be a Transmeta chip) to their heart's content until it alligns with the bus requirements for the MP855x chip line next year.

    The rumor about the next Mobo not supporting OS 9 may point toward a 64 Bit optimized architecture, It'd cause some havoc but vastly increase scaling and RAM capabilities.

    2 weeks to go. Keep it civil guys.:D ;)
  14. Backtothemac macrumors 601


    Jan 3, 2002
    San Destin Florida
    Oh sweet Jesus, the end is near. There is the proof. Mischief is saying that folks should keep it civil.

    The king of all that is pie.

    Say it isn't so.

    Whipes tear from face.....
  15. Grokgod macrumors 6502a


    Feb 26, 2002
    Deep within the heart of madness!

    I hear your formative and confident statement of the 1.4's coming out at MWNY.

    I remember you saying this before and also talking about a possible source?

    Is there anything else that you can tell us about why you feel so sure about this event? Now that we are closer.?
  16. tjwett macrumors 68000


    May 6, 2002
    Brooklyn, NYC

    this is not true DDR. true DDR needs the ram AND bus. you will not see the same performance as if the bus was 266 and the ram used was 133 DDR.
  17. Catfish_Man macrumors 68030


    Sep 13, 2001
    Portland, OR
    Just to clear a few things up...


    1) The current G4 does NOT effectively use DDR ram. This includes the XServe. The only gains the XServe gets out of DDR is for DMA tasks, and a slight latency decrease. This is still useful, just not as useful. The G4's bus can get about 1.05GB/sec, DDR can provide 2.1GB/sec.

    2) The embedded community (the G4's primary buyers) LIKE the bus just as it is. To support DDR properly the bus would have to be changed in ways that they wouldn't like (info from BadAndy's posts on the Arstechnica Macintoshian Achia. BA is an embedded programmer who works with G4s a lot and is very knowledgeable).

    3) The current bus can be run faster than 133MHz SDR, but apparently it can only be done properly in single processor configurations. I can't remember why. It's not really supposed to run at that speed but it can do it just fine.

    4) A new G4 MAY support DDR, I'm just not quite sure how. The G4 at MWNY is almost certain not to be the 7455.

    5) The G5 is unlikely to have a memory bus. It's much more likely to have an on chip DDR controller and use HyperTransport or RapidIO for everything else (similar to AMD's Hammer). This is a good thing. A very good thing.

    corrections/additions welcome.
  18. PFY macrumors newbie

    May 22, 2002
    There has long been talk of an MPX+ bus which is supposed to run at double the speed of the current MPX bus used by the current crop of G4s. So if Motorola has the next revision of the G4 ready we might still see a big increase in speed!
    If the new G4s reach 1.5GHz with this new bus they might even be as fast as an AthlonXP.
  19. topicolo macrumors 68000


    Jun 4, 2002
    Ottawa, ON
    Of course a DDR bus exists! DDR stands for Double Data Rate and if a fsb transfers data at both the peaks and the troughs of its frequency, it is a DDR bus. Athlons use a DDR Bus; the 200 or 266 is really just a 100 or 133Mhz DDR bus. That's why it only says 100 or 133 as the standard on an athlon mobo when you try to overclock it. P4s use a QDR bus (Quad data Rate) at either 100 or 133Mhz with a QDR "force multiplier" to make it 400 or 533Mhz.
  20. G4scott macrumors 68020


    Jan 9, 2002
    Austin, TX
    Re: MWNY DDR RAM? Actual G4 does NOT support DDRam at higher Bus speed!!!

    Those specs are only for the MPC7455... You never know if a better chip in the future will have a 200+ mhz DDR fsb speed.

    Besides, all that bs about pentium 4's with a 400 mhz bus is stupid... I had a friend say that his computer had a 400mhz bus, but I told him that intel just says that its doubled to try to sell more... I hate bad marketing... Someday, it's going to bring down m$, intel, and hopefully dell, just like bad business practices brought down enron, and are bringing down worldcom. Another one bites the dust...
  21. Backtothemac macrumors 601


    Jan 3, 2002
    San Destin Florida
    Well, I obviously cannot tell you the persons name and position, but they are very accurate with their information. They have been known to pull a prank on me, but I don't believe that this is one. They have been steady in this since like January actually. They said that July would be the big change in the G4's, and then in February came to the table with specs. I personally believe them, and would be shocked if they were wrong. SHOCKED!

    Now, DDR bus?!?!?! No, it is a force multiplier. Call it what it is. And the Athlon operates at a true 200 or 266MHZ, without force multipliers. The quad multiplier that you speak of on the PIV is a friggin joke. That is why the Athlon can kick A$$ on a PIV. It takes them 800MHZ to match an Athlon. Sad. Intel blows.
  22. Sun Baked macrumors G5

    Sun Baked

    May 19, 2002
    I thought the CPU was supporting the MPX bus protocols and the bridge chips that were providing the IO support (ie - PCI, SD/DDR, ROM, ATA, etc.)

    While the embedded chips have a limited single chip solution having some of the bridge chip solutions built-in and would natively support 133MHz memory on a single chip.

    And I also though the FSB on Intels part was part of the Rambus fiasco, and an attempt to take advantage of high MHz Rambus memory by extending a high MHz path from the CPU through the chipset to memory. But since intel has plugged the Rambus path with DDR the Intel 850 chipset looks a lot like the standard MPX bridge chips now (at least to IO which is the bottleneck).
  23. solvs macrumors 603


    Jun 25, 2002
    LaLaLand, CA
    Just to clarify

    Intel Pentium 4: 100/133 MHz FSB Quad Pumped (x4) = 400/533 MHz. 800 MHz RAMBUS (Also, I believe, Quad Pumped to = 800).

    AMD Durons: 100 MHz FSB DDR (x2) = 200 MHz
    AMD Athlon: 133 MHz FSB DDR (x2) = 266 MHz
    Both allowing for anywhere from 133 MHz SDRAM, to 200/266/333 DDR RAM (100/133/166 x2) memory.

    Anyone else notice that the RAM for all of the "low-end" Macs with the 100 MHz FSB is PC133 (133 MHz).

    Or that I'm typing this on an Intel (ugh, don't get me started)Celeron with a 66 MHz FSB running 133 MHz memory. Or my friends Celeron with a 100 MHz FSB running 266 MHz DDR RAM.

    The real bottle neck is in the Hard Drive area. When are we going to get some real ATA/133 performance. Or Serial ATA (it exists, I've seen the controllers, they're ready to go. Check SIIG's website. 150 MB/sec). At least give us the ability to have hard drives over 128-137 GBs (the current limit for ATA/66/100) with out having to buy an ATA/133 IDE card on my, soon to be purchased, :) brand new Powermac Tower. I know Apple wants to sell computers and you can't completely future proof them, but it's called planning ahead people.

    Either they have a crappy CPU that can't keep up with the competition and they need to speed up everything else around it, or they have a kick-a** CPU that's chocking on bottlenecks. Who needs raw GHz when you have a 166 MHz (especially DDR to 333) FSB and support for the CURRENT memory and hard drive specifications. I've checked. Motorola's latest G4 can run at a 166 MHz FSB, even if there are heat issues (it's not like Macs have the same limitations of the embedded market). And the IBM G3's can run at a 200 MHz FSB (not 100 DDR x2, but 200 MHz!!!).

    Please don't give me that old "Current-drives-can't-even-max-out-at-66MB/sec" arguement. Western Digital has a 200 GB 7,200 drive coming out in July (drools), and even if the new Towers have ATA/100, you might as well buy a 120 GB Hard Drive. That's why I can't buy an iMac or eMac to save some $$$ in the mean time. Also, I do video, and image editing and I need the space and the speed, but I am on a budget here. I'm not even talking about built in raid support - as nice as that would be. ;)

    My prediction, they must be holding out on shipping the XServe until Macworld. New G4's at 1.2 to 1.4 GHz, to be included in the XServe at current prices. Towers are similar in specs - ATA/100, 120 GB Hard Drives, 266 DDR RAM (although ATA/133, 333 DDR RAM, 166 MHz FSB, FW 2, USB 2, etc. would be nice, but I'm not getting my hopes up. Again). No TRUE G5s. Yet.

    Okay, I'm done. You can tell I don't have a life. But, I guess well all see what happens in a couple of weeks.

    If those of us who need lives, or need to get work done, can wait that long.
  24. topicolo macrumors 68000


    Jun 4, 2002
    Ottawa, ON
    Re: Just to clarify

    THANK YOU!! Someone who agrees with me! you may not have a life, but you sure know what you're talking about. ;)
  25. Chryx macrumors regular

    Jul 8, 2002
    Here, have a cluestick.. please beat yourself with it.. :)

    the Athlon's frontside bus is 100Mhz (in the case of the original Slot A Athlons and the initial Thunderbird core Athlon's, and the Duron for that matter) or 133Mhz (>1Ghz Tbirds/AthlonXP/AthlonMP) double data rate. incase the concept of DDR is lost on you, here's a diagram :-

    a , indicates a piece of data
    /--\ = clockpulse
    ___ = gap between clockpulses

    Single Data Rate :


    Double Data Rate :


    The Pentium 4 on the other hand, uses a 100/133Mhz Quad pumped bus. the diagram for this looks something like.


    the command rate in all cases remains on the the initial rising edge at 100 or 133Mhz, but data can be transferred on all cycles. (except of course the cycles being used for command data.)

    Oh, and just WHAT THE HELL is a "Force Multiplier" ?, maybe I should go play Jedi Outcast again?.. hmm?

    The Athlon kicks the P4's ass for the same reason that the G4 _can_ kick the Pentium 3's ass, it's a more efficient core, although it is beginning to feel the limits of it's 2.1GB/s memory interface at the high end, the 2.2Ghz+ Pentium 4's (particularly the 133QDR parts) begin to pull away from the >1.73Ghz AthlonXP's simply because the P4's massive clock for clock inefficiency is outweighed by

    a) it's clockspeed lead
    b) the huge memory subsystem keeping the processor pipeline fed

    BTW, Solvs, PC800 Rdram is 400Mhz DDR, PC1066 Rdram is 533Mhz DDR (it scales high in clockspeed because it's such a narrow bus)

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