Apple would have to come up with a killer system controller because of the variable speed of FSB. A G4 for instance has a set in stone 133, 150 or 167Mhz FSB supporting SDRAM, the L3 is 1 quarter the cpu speed with DDR SRAM. The PPC970 has no L3 support but an FSB of 1 quarter the cpu speed with support DDR SDRAM. Let's assume Apple are going to standardise on 400Mhz DDR II (if it comes out), these are kind of mismatched FSB and RAM speeds they'd have to deal with in whatever system controller they come up with : 1.4Ghz 350Mhz FSB x 2 with 400Mhz DDR II = FSB x 1.14 x 2 or 6.4Gb/s 1.6Ghz 400Mhz FSB x 2 with 400Mhz DDR II = FSB x 2 or 6.4Gb/s 1.8Ghz 450Mhz FSB x 2 with 400Mhz DDR II = FSB x 1.7 or 6.4Gb/s Maybe they could even add a L3 on the system controller, a couple of Mb/s of DDR SRAM between the controller and the cpu on the models above 1.6Ghz could add a little extra performance. I know they've had DDR 266 and 333 chipsets for the Pentium 4 for quite a while and that's either got a 100Mhz x 4 or 133Mhz x 4 FSB running on unmatched speeds of DDR RAM. It could be the same for the system controller Apple would have to use with the PPC970 except the controller would have to automatically compensate for the difference between FSB and RAM speed instead of only having to choose between either 400Mhz or 533Mhz like the Pentium 4 chipsets probably do. Does anyone know enough about cpu/chipset design to explain how this might work ?