Originally posted by dstorey
As the 970's don't support Hyper Transport, and Apple had to use a bridge chip to connect it to their hypertransport Mobo, doesn't anyone know if the system takes a performance hit due to this?
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.Originally posted by dstorey
As the 970's don't support Hyper Transport, and Apple had to use a bridge chip to connect it to their hypertransport Mobo, doesn't anyone know if the system takes a performance hit due to this?
Originally posted by NuVector
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.
Similarly there was a general exposition of memory latency issues
(which are of course directly related to SMT issues), and in response
to a question from the floor the advantages of integrated memory
controllers were warmly compared to Opteron, and again the
"roadmapish" statement made that IBM will provide such, but no time given.
Originally posted by NuVector
Apple didn't have to use a "bridge chip", they used a memory controller. Even if the chip supported HT, it'd still have to talk to Apple's memory controller and the bus speed is determined by the CPU not the other way around, so the short answer to your question is: no.
Originally posted by Sun Baked:
IBM has said they would be supporting a wide range of technologies in their custom ASIC business.
They even list HT as one of the available Blue Logic Cores for the custome ASIC division.
http://www-3.ibm.com/chips/products/asics/products/cores/corelist.html
Would almost expect them to join the consortium...
Originally posted by dstorey
So if IBM re-engineer their powerpc family, as the article suggests they will be, then what advantages, if any, will it give? I guess the northbridge and southbridge will be able to conect via hyper transport than, as well as the rest, creating the hyper transport ring that i've heard mentioned...but i guess this will be no faster..maybe just easier to engineer and produce?