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spaceballl

macrumors 68030
Original poster
Nov 2, 2003
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I read a bunch of rumors that Apple was working to optimize for SSE4 instructions for the new batch of Intel chips coming out - does anyone know if this happened?
 
I read a bunch of rumors that Apple was working to optimize for SSE4 instructions for the new batch of Intel chips coming out - does anyone know if this happened?

the libvDSP.dylib component in the Accelerate framework was updated in 10.5.2, among others, so perhaps they got it in. You'll know for sure when it appears in the developer tools/documentation.
 
I read a bunch of rumors that Apple was working to optimize for SSE4 instructions for the new batch of Intel chips coming out - does anyone know if this happened?

I doubt it. IIUC SSE4 is just a batch of new CPU instructions that the new Intel CPUs support. In order to take advantage of that, gcc (XCode c/c++/objective c compiler) would have to be updated to emit these new instructions. If Apple has an internal version of gcc that understands these instructions they may have used it. But, that would only apply to OS code, code that you run (3rd party software or whatever) surely wouldn't be comiled with a compiler that apple hasn't released yet.
 
I doubt it. IIUC SSE4 is just a batch of new CPU instructions that the new Intel CPUs support. In order to take advantage of that, gcc (XCode c/c++/objective c compiler) would have to be updated to emit these new instructions. If Apple has an internal version of gcc that understands these instructions they may have used it. But, that would only apply to OS code, code that you run (3rd party software or whatever) surely wouldn't be comiled with a compiler that apple hasn't released yet.

That is wrong. You only need an assembler, and if you are an operating system manufacturer, you can do it in binary/machine-code if you didn't have time to hack your assembler.

That is the whole point of the Accelerate framework.

However, if none of the existing Accelerate APIs can make any practical use of the SSE4 instructions, it won't be useful until the new APIs are published.
 
That is wrong. You only need an assembler, and if you are an operating system manufacturer, you can do it in binary/machine-code if you didn't have time to hack your assembler.

That is the whole point of the Accelerate framework.

However, if none of the existing Accelerate APIs can make any practical use of the SSE4 instructions, it won't be useful until the new APIs are published.

The accelerate framework sounds pretty neat. So the answer to the original question rests on several further questions:

- Do the accelerate APIs do anything which could take advantage of SSE4 instructions?
- Did Apple update code within the accelerate framework to use SSE4 instructions.
- Does the software you're interested in spend significant time in accelerate framework library code which is likely to be faster with SSE4 support.

And:

- When you install Mac OS 10.5.2, does it tailor the binaries to the specific CPU you're using? libvDSP looks like this:

/System/Library/Frameworks/Accelerate.framework/Versions/A/Frameworks/vecLib.framework/Versions/A
office:A kelly$ file libvDSP.dylib
libvDSP.dylib: Mach-O universal binary with 4 architectures
libvDSP.dylib (for architecture i386): Mach-O dynamically linked shared library i386
libvDSP.dylib (for architecture ppc7400): Mach-O dynamically linked shared library ppc
libvDSP.dylib (for architecture ppc64): Mach-O 64-bit dynamically linked shared library ppc64
libvDSP.dylib (for architecture x86_64): Mach-O 64-bit dynamically linked shared library x86_64

It seems like we need another couple of entries: (for architecture i386 supporting SSE4) and (for architecture x86_64 supporting SSE4). Without this, how does a binary with SSE4 support work on an intel chip which doesn't support the instruction?
 
It seems like we need another couple of entries: (for architecture i386 supporting SSE4) and (for architecture x86_64 supporting SSE4). Without this, how does a binary with SSE4 support work on an intel chip which doesn't support the instruction?

SSE4 is just a subset of the (ever changing) i386 & AMD64 architectures. It doesn't qualify as an architecture. The software can call the x86 CPUID instruction, which returns a value that indicates what features are supported by the CPU. Older CPUs return zeros in the areas reserved for future capabilities, while software ignores features it does not understand. When software sees that SSE4 is supported, it can run a different version of certain functions that make use of those instructions, while the generic version does not.
 
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