Somewhere on the forum, I remember a discussion taking place over the 2.7GHz Power PC's being over-clocked. I have found this article, that suggests otherwise.
IBM actually designed the 970FX microprocessor to operate at speeds of up to 2.7GHz. Here is some proof.
The 64-bitPowerPC 970FX microprocessor builds on the proven 64-bit IBM Power Architecture family and is suited to embedded applications including imaging and networking, and provides new levels of performance and power management for the embedded marketplace. Designed to run at frequencies up to 2.7 GHz, the PowerPC 970FX includes a 512KB L2 cache, provides native 64-bit and 32-bit application compatibility and uses a high bandwidth processor bus capable of delivering up to 7.1 GB/s to keep the processor core and the SIMD/Vector engine fed with data. The processor core can dispatch five instructions per cycle, and issue one instruction per cycle to each of its ten execution units, including two fixed point, two floating point, two load store, two vector and two system units. The L1 instruction cache holds 64 KB, the L1 data cache holds 32 KB, and each processor has its own dedicated 1MB L2 cache.
This extract was taken from
http://www-1.ibm.com/press/PressSer...lass&SESSIONKEY=any&WindowTitle=Press+Release
Sorry if this as already been posted.
IBM actually designed the 970FX microprocessor to operate at speeds of up to 2.7GHz. Here is some proof.
The 64-bitPowerPC 970FX microprocessor builds on the proven 64-bit IBM Power Architecture family and is suited to embedded applications including imaging and networking, and provides new levels of performance and power management for the embedded marketplace. Designed to run at frequencies up to 2.7 GHz, the PowerPC 970FX includes a 512KB L2 cache, provides native 64-bit and 32-bit application compatibility and uses a high bandwidth processor bus capable of delivering up to 7.1 GB/s to keep the processor core and the SIMD/Vector engine fed with data. The processor core can dispatch five instructions per cycle, and issue one instruction per cycle to each of its ten execution units, including two fixed point, two floating point, two load store, two vector and two system units. The L1 instruction cache holds 64 KB, the L1 data cache holds 32 KB, and each processor has its own dedicated 1MB L2 cache.
This extract was taken from
http://www-1.ibm.com/press/PressSer...lass&SESSIONKEY=any&WindowTitle=Press+Release
Sorry if this as already been posted.