I noticed in the specs for the new Mac Pros that there is 8MB of fully shared L3 cache per processor, but no mention of L2 cache. Previous gen Mac Pros, had 12MB of L2 cache per processor, but no mention of L3 cache. I did some searching to see if I could understand the difference, but maybe someone here has a better explanation.
(from wikipedia)
Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.
As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. For example, the Alpha 21164 (1995) had a 96 KB on-die L3 cache, the IBM POWER4 (2001) had a 256 MB L3 cache off-chip, shared among several processors, the Itanium 2 (2003) had a 6 MB unified level 3 (L3) cache on-die, Intel's Xeon MP product code-named "Tulsa" (2006) features 16 MiB of on-die L3 cache shared between two processor cores, the AMD Phenom (2007) has a 2 MB on-die L3 cache and the Intel Core i7 (2008) has an 8 MB on-die unified L3 cache that is inclusive, shared by all cores. The benefits of an L3 cache depend on the application's access patterns.
(from wikipedia)
Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.
As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. For example, the Alpha 21164 (1995) had a 96 KB on-die L3 cache, the IBM POWER4 (2001) had a 256 MB L3 cache off-chip, shared among several processors, the Itanium 2 (2003) had a 6 MB unified level 3 (L3) cache on-die, Intel's Xeon MP product code-named "Tulsa" (2006) features 16 MiB of on-die L3 cache shared between two processor cores, the AMD Phenom (2007) has a 2 MB on-die L3 cache and the Intel Core i7 (2008) has an 8 MB on-die unified L3 cache that is inclusive, shared by all cores. The benefits of an L3 cache depend on the application's access patterns.