Back in the day when the PowerMac had just eclipsed the 1GHz mark, rumors were flying everywhere that an updated G4 core would feature a number of enhancements outside of a megahertz jump. The most significant of these were the support for a higher FSB, an inclusion of double the L2 cache, and double the L3 cache. All of these features would be brought on thanks to the switch to a smaller manufacturing process, allowing these a higher clock rate and larger cache sizes.
The FSB support can only be assumed. Altivec is certainly starved as it is, and even without Altivec, a machine at 1.4GHz should not be on a 166MHz system bus. The rumors of a double-pumped 400MHz system bus are, I'd guess, true.
The L2 cache will almost certainly receive a boost with the extra space available on the chip. It only makes sense that 512K of L2 cache would wind up on the G4. Again, I'd have to believe these rumors are true.
But what about the L3 cache? This is a tough call, because with the extra bandwidth from the higher FSB, the effect of a costly L3 cache is minimal. However, if Motorola were to double the size of the L3 cache, bringing it to 4MB, systems would have the effect of a large L2 cache, a large L3 cache, AND a relatively quick FSB. It'd be a triple whammy.
In fact, if all three improvements were made, and the chip were able to clock to 1.8GHz on the current process, the G4 would easily rival IBM's G5. The G5 would have a similar L2 cache, but would lack an L3 cache. And though the G5 has a tremendously quick FSB, it is definitely a more complicated processor, and pays more heavily on branch prediction failure. In short, it's not as clean as the G4 on some levels. Added to this is the G5's relatively weak Altivec unit, and the G4 is definitely staying for a while.
The FSB support can only be assumed. Altivec is certainly starved as it is, and even without Altivec, a machine at 1.4GHz should not be on a 166MHz system bus. The rumors of a double-pumped 400MHz system bus are, I'd guess, true.
The L2 cache will almost certainly receive a boost with the extra space available on the chip. It only makes sense that 512K of L2 cache would wind up on the G4. Again, I'd have to believe these rumors are true.
But what about the L3 cache? This is a tough call, because with the extra bandwidth from the higher FSB, the effect of a costly L3 cache is minimal. However, if Motorola were to double the size of the L3 cache, bringing it to 4MB, systems would have the effect of a large L2 cache, a large L3 cache, AND a relatively quick FSB. It'd be a triple whammy.
In fact, if all three improvements were made, and the chip were able to clock to 1.8GHz on the current process, the G4 would easily rival IBM's G5. The G5 would have a similar L2 cache, but would lack an L3 cache. And though the G5 has a tremendously quick FSB, it is definitely a more complicated processor, and pays more heavily on branch prediction failure. In short, it's not as clean as the G4 on some levels. Added to this is the G5's relatively weak Altivec unit, and the G4 is definitely staying for a while.
