G4 v. P4 Comparison

[AlejandroGonzo]

There was an interesting article and thread concerning a comparison between the G4e and P4 at ars technica. It's old (oh well, I want to vent), but I learned a lot and wanted to share. It can be found here: http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=174096756&m=7500907803&r=7500907803

To summary, in a debate between Mac and PC techies, both sides finally agreed that the G4 was 33% faster per clock cycle than a P3 and 69% faster than a P4. The P3 achieves more work per cycle, but the P4 can achieve clock speeds high enough to negate this advantage and thus create a faster system.

The main disadvantage to the G4 is that it is lacking DDR Ram and is thus starved for information.

Therefore, if Apple releases a 1.4 GHz G4 system in NY, the P4 equivalent would be a 2.366 GHz processor. At 1.5 GHz, the G4 is equivalent to a P4 2.53 GHz. Also note however, that this is excluding the performance gains due to DDR Ram and to dual processor systems.

Cool Huh!

Now I won't feel so bad if I get a Powerbook G4. I think I will wait for 1GHz though (and DDR?).

Should Apple move to an AMD style naming system for their computers, multiplying the megahertz of a particular system by 1.69? Also, since P4 mobiles are slower than their desktop counterparts, any thoughts as to how much more work is done per cycle by the G4 as opposed to these systems? What about AMD chips?

 

[firewire2001]

hey.. thats a pretty cool article...

however, i think this is sort of theoretical in a way -- i mean, different processors can achieve different stuff in one cycle, but overall certain processors can process more data more quickly than the other that processed more data in just one cycle..

has anyone seen RECENT benchmark tests for programs like photoshop, or games like quake3?

 

[Malus120]

I agree about the G4 being starved for data thing. i bet if Apple got a bit faster proccesors(and or went duel in all models) added DDR Ram and a faster FSB we'd be kicken some Pentium Ass.

 

[menoinjun]

And yet this means nothing for real world performance.

If OS X was as fast as windows (and it almost is) then this would mean more. But for now, we can all say that the G4 is faster than the P4, and have only stats to prove it. Stats mean little in the consumer market.

Hopefully OS X.2 will solve all the problems.

-Pete

 

[bacon]

Re: G4 v. P4 Comparison

Originally posted by AlejandroGonzo
To summary, in a debate between Mac and PC techies, both sides finally agreed that the G4 was 33% faster per clock cycle than a P3 and 69% faster than a P4. The P3 achieves more work per cycle, but the P4 can achieve clock speeds high enough to negate this advantage and thus create a faster system.

From what I gather, the next G4 chip isn't going to be directly comparable to the current chip, i.e., it's not going to be the same chip running at a higher clock. Motorola is supposedly adding more pipeline stages which means the chip is being redesigned to some extent. We'll have to wait and see how the new PowerMacs perform, which is exactly what I'm doing.

 

[G5orbust]

Heres the specs to compare too.

P4
Top speed: 2.53 Ghz
Bus speed: 533 MHz/400 MHz
Memory types: SDRAM/DDR-SDRAM/RDRAM
L2 Cache: 512 K
L3 cache: N/A
Micron Process: .13µ
Maximum Memory: 4 GB adressable
special features: quad pumped bus

G4
Top speed: 1 Ghz
Bus Speed: 133 Mhz/ 266 Mhz (xserve)
Memory types: SDRAM/DDR-SDRAM (xserve)
L2 Cache: 256 K
L3 Cache: 2 Mb DDR SDRAM @ 200 Mhz
Micron process: .13 µ
Maximum memory: 1.5 GB adressable
special features: Altivec, 128 bit processing



Just thought this might help

 

[decimal]

Originally posted by G5orbust
Heres the specs to compare too.

G4
Micron process: .13 µ

Just thought this might help

just for the record
G4 uses the 0.18 µ process


http://e-www.motorola.com/webapp/sps/site/taxonomy.jsp?nodeId=03M943030450467M98653

 

[Catfish_Man]

A few additions/corrections...

Originally posted by G5orbust
Heres the specs to compare too.

P4
Top speed: 2.53 Ghz
Bus speed: 533 MHz/400 MHz
Memory types: SDRAM/DDR-SDRAM/RDRAM
L2 Cache: 512 K
L3 cache: N/A
Micron Process: .13µ
Maximum Memory: 4 GB adressable
special features: quad pumped bus

G4
Top speed: 1 Ghz
Bus Speed: 133 Mhz/ 266 Mhz (xserve)
Memory types: SDRAM/DDR-SDRAM (xserve)
L2 Cache: 256 K
L3 Cache: 2 Mb DDR SDRAM @ 200 Mhz
Micron process: .13 µ
Maximum memory: 1.5 GB adressable
special features: Altivec, 128 bit processing



Just thought this might help

...the XServe has a 133MHz DDR memory controller, and a 133MHz SDR system bus. The G4 is made on a .18 micron SOI process. The L3 cache on a G4 is 1/4 the clockspeed, so 250MHz (500 effective). Both the P4 and the G4 can do 128 bit vector math (Altivec, SSE, MMX, SSE2), the G4 just has a much superior way of doing it (4 dedicated pipelines to 1 shared pipeline). The P4 has a very small but quite innovative L1 cache called a trace cache that eliminates some of the overhead of x86. PowerPC (the G4 in this case) has flat registers, x86 has stack based registers. The P4's simple integer pipelines run at twice the normal clock speed. The quad-pumped bus is actually two 133MHz DDR buses running together to act as one 533MHz bus. The P4 has a 20 stage pipeline (afaik), the G4+ (7450, 7451, 7455, 7440, 7441, 7445) has a 7 stage one. The old G4 (7400, 7410) has a 4 stage pipeline. The G4 has 64k of L1 cache. The G4 has a lot more registers (I'm not quite sure how many more).

 

[rice_web]

And while we're throwing around numbers:

750FX from IBM:
- 512K L2 Cache
- 4 pipeline stages
- up to 200MHz system bus
- sticking to its RISC status

New PowerPC G4 from Motorola (rumored):
- 512K L2 Cache
- 2 or 4MB L3 Cache
- 12 pipeline stages
- 166MHz system bus or 266MHz system bus
- becoming more CISC-like

 

[decimal]

Re: A few additions/corrections...

Originally posted by Catfish_Man


...the XServe has a 133MHz DDR memory controller, and a 133MHz SDR system bus. The G4 is made on a .18 micron SOI process. The L3 cache on a G4 is ....

Again I see from mot data that some of the G4s actually do not use SOI technology (7450, 7451). This is interesting especially since the 7445 uses SOI. I read somewhere TiBooks use 7450,7451. Cant help wondering if SOI creates problems with mobile chips....

 

[Catfish_Man]

Re: Re: A few additions/corrections...

Originally posted by decimal


Again I see from mot data that some of the G4s actually do not use SOI technology (7450, 7451). This is interesting especially since the 7445 uses SOI. I read somewhere TiBooks use 7450,7451. Cant help wondering if SOI creates problems with mobile chips....

7400 = G4
7410 = low power G4
7450 = G4+
7440 = low power G4+
7451/7441 = bug fixes
7455/7445 = SOI, DDR L3 cache

The new powerbooks use 7455s, same as the new powermacs. I expected a 7445 in the TiBook, but apparently SOI created a great enough heat/power savings that they could keep the L3 cache.

New PowerPC G4 from Motorola (rumored):
- 512K L2 Cache
- 2 or 4MB L3 Cache
- 12 pipeline stages
- 166MHz system bus or 266MHz system bus
- becoming more CISC-like

I hadn't heard the 12 pipeline stages before, where'd you find it? A 166 bus would be interesting because it would be 166 SDR, while a 266 would be 133 DDR. I agree about the L2 cache (I would expect that the next G4 will be transitioning to .13 micron, which gives them more room). I'm not sure about the L3 cache, if it uses sdram maybe, if it's sram like the L2 then it would be too expensive. My guess is that we won't get pipeline changes, but will get .13 micron, 512k L2 cache, and a DDR bus. All of these should provide a very nice speed boost, as well as letting Motorola be the first to market with a high end chip on .13 micron SOI (neither AMD nor Intel has it yet).

 

[rice_web]

The 12 pipeline stages rumors has been floating around for a long time, although it hasn't been talked of much.

I believe that the Register and MacOS Rumors did stories on it.

As it stands, the G4 would have a difficult time scaling beyond its current levels. So, with .13 micron manufacturing and 12 pipeline stages, the G4 could scale like the P4 (and possibly to P4 levels).

Here's the way I look at it:

When AMD switch to .18 micron manufacturing, they were able to release faster processors. The same has applied to all manufacturers (even Moto and IBM).

Remember the jump from 4 to 7 pipeline stages? The G4 was able to scale from 500MHz to currently 1GHz. That's amazing. The G4 was able to double its clock speed by not even doubling the pipeline stages. So, a jump from 7 to 12 would yield nearly the same results in itself.

With .13micron manufacturing and 12 pipeline stages, the G4 could easily (in my opinion) scale to 2GHz.

As for the L3 cache, that's largely wishful thinking (however, I believe I read something on it one time)

 

[AlejandroGonzo]

Should Apple go to an AMD style naming scheme? It makes sense to me since the G4 does 69% more work per clock cycle. Sticking a big number next to the processor can only help with sales.

 

[Cappy]

Originally posted by AlejandroGonzo
Should Apple go to an AMD style naming scheme? It makes sense to me since the G4 does 69% more work per clock cycle. Sticking a big number next to the processor can only help with sales.

It really depends on what markets Apple is really wanting to target. For the highend market I don't think it matters much. People already know if a Mac or a PC is really the best solution without being misled by mhz numbers. The consumer models though might be able to benefit from an AMD-style numbering scheme.

 

[rice_web]

Well, I could certainly see Apple marketing the PowerMac as the "PowerMac 2000", seeing as it has two heads. But, I just don't think it's Apple's style to do that. If it was, they would have labeled the XServe's system bus as 266MHz.

 

[Malus120]

Originally posted by rice_web
The 12 pipeline stages rumors has been floating around for a long time, although it hasn't been talked of much.

I believe that the Register and MacOS Rumors did stories on it.

As it stands, the G4 would have a difficult time scaling beyond its current levels. So, with .13 micron manufacturing and 12 pipeline stages, the G4 could scale like the P4 (and possibly to P4 levels).

Here's the way I look at it:

When AMD switch to .18 micron manufacturing, they were able to release faster processors. The same has applied to all manufacturers (even Moto and IBM).

Remember the jump from 4 to 7 pipeline stages? The G4 was able to scale from 500MHz to currently 1GHz. That's amazing. The G4 was able to double its clock speed by not even doubling the pipeline stages. So, a jump from 7 to 12 would yield nearly the same results in itself.

With .13micron manufacturing and 12 pipeline stages, the G4 could easily (in my opinion) scale to 2GHz.

As for the L3 cache, that's largely wishful thinking (however, I believe I read something on it one time)

You make good points BUT
I dont think its always worth it too increase your pipeine stages just to get more clockspeed. For instance when intel released its 20 Pline stages P4 it was actually slower clock for clock than a P3 of course it didnt look like a huge amount of slowdown because the bus and ram were so much faster than on P3 systems, but there still was a slowdown. Also when Moto switched to a 7 Pipeline stage G4 it was actually slower in a few areas than the old 7400s, now granted i agree that this needed to be done as a chip redesign seemed to be the only way the G4 woud go anywhere, but still its not always the best way to go. Macworld predicted that the current G4 if taken down to .13 micron process could probably scale to at least 1.3Ghz if not higher. Not to mention that the G5 is supposed to scale over 2GHZ and its only running a 10 stage pipeline. Heck look at IBM's newest G3 which scale to 1Ghz while still keeping the old 4 pipeline stage design of way back when. Now granted im betting from looking at the specs on it that IBM's current design is fairly close to maxed out but i feel like Moto could learn something from that and try to keep the G4's pipeline stages under 10. I believe that with a little work they could easily scale the currant G4's to 1.4-1.7 which should easily be enough to hold off until we get the G5s(now before all you people Flame me to death telling me how the P4 is at 2.5 keep in mind that AMDs fastest Athalon is still only around 1.7 and it is easily as fastest as all but the top of the line P4 and its running on a SLOWER bus and Ram than the P4). I remember when there were rumers that the G4 would go to a 14 Stage design and i was just like HELL NO that would basically kill most of our clock for clock advantage. I just believe that moto and apple should Exhaust all other ways of increasing clock speed and performance(faster Bus and DDR ram anyone) before resulting to redesiging the G4 with a longer pipeline, otherwise there chips really wont be that much better than Intels now will they?

 

[cb911]

Ars is always good for tech stuff, pretty good reading.

oh well, thats sort of brought back my confidence in Apple. although we'll still have to wait and see what happens when the 3GHz P4 is released...

 

[Catfish_Man]

The real threat isn't Intel right now...

Originally posted by cb911
Ars is always good for tech stuff, pretty good reading.

oh well, thats sort of brought back my confidence in Apple. although we'll still have to wait and see what happens when the 3GHz P4 is released...

...(although I must admit, Prescott is looking pretty impressive), the real threat is AMD's Hammer. As far as I can tell Hammer is almost identical to what I'm expecting for the G5. .13 micron, on chip DDR controller, HyperTransport (RapidIO for the G5, but they're pretty similar).