Apple claim and I don't doubt that the new G5 supports up to 8GB of DDR 400. My misunderstanding however is that Apple claim that G5 has a memory bandwidth of 6.4GB/s which I dont doubt, but is however twice what DDR 400 can offer, being 3.2 GB/s hence its other name DDR 3200.
This leads me to the assumption that the new G5 runs Dual Channel DDR (developed by Nvidia.) Hence 4GB per channel if the memory is shared between both the processors, or 2GB per channel per processor to make up the 6.4GB/s bandwidth.
These configurations are the only way without using the now defunct RD RAM (which had a frequencies of up to 1066MHz and a bandwidth of 8GB/s) to come even close to making use of the amazingly fast FSB of 1000MHz.
If the second assumption is true about each processor accessing its own bank of ram Apple hasn't broken the 4GB barrier per processor.
Either way these insights show that the 8GB of DDR 400 may not be all its cracked up to be.
This leads me to the assumption that the new G5 runs Dual Channel DDR (developed by Nvidia.) Hence 4GB per channel if the memory is shared between both the processors, or 2GB per channel per processor to make up the 6.4GB/s bandwidth.
These configurations are the only way without using the now defunct RD RAM (which had a frequencies of up to 1066MHz and a bandwidth of 8GB/s) to come even close to making use of the amazingly fast FSB of 1000MHz.
If the second assumption is true about each processor accessing its own bank of ram Apple hasn't broken the 4GB barrier per processor.
Either way these insights show that the 8GB of DDR 400 may not be all its cracked up to be.