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GPUL2 and the 970

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Apr 12, 2001
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MacEdition's Naked Mole Rat report clarifies some information about the upcoming GPUL2 which was referenced by eWeek as a replacement to the 970 (GPUL) by Mid-2004.

According to MacEdition, the GPUL2 is essentially the same architecture as the PPC 970, and that the Power5 derivative chip is a separate project. (MacEdition article).


Based on the timing of release, the GPUL2 would presumably be the processor to take Apple to 3GHz by next year. If so, it may cast some doubts on this ambitious report.
 
Article Link
https://www.macrumors.com/2003/07/28/powerpc-future-gpul2-and-the-970/
Hmmm...... So a G5+?
The 970 shrunk? Allowing higher clock speeds?
Not bad news. As long as there is news about the Mac's future processors!

Maybe the P5UL will be the G6....:cool:
 
So GPUL2 is the 970 @ 90nm, I can live with that. :) The 980 was never really confirmed anyway, so this doesn't trouble me much. I don't think that this eliminates the possibility of a 980 either.

Maybe there should be a neutral option when rating stories. :)
 
I doubt they will call this the G6.

But, a Dual 3Ghz would really be a 'kick-ass' machine. ;)
 
Re: GPUL2 and the 970

This can only be taken as good news. It means that the 970 will have some life in it beyond the first rev.

Of course this now means we can all speculate on what this rev will contain. Seeing that Apple has a big influence here are a couple of pridictions:

1.
An on board interface to DDSDRAM. The most obvious reason would be for a simpler implementation of PowerBooks and low cost machines for Apple. I'm still a bit relucatnat to believe that the current G5 chip set will end up in a Power Book, this would be one answer to squeezing everything in.

2.
An increase in the onboard L2 cache. While maybe not an issue at the moment, as the processor begins to outstrip the ability of the memory bus to feed it, it will become more important. While doubling would be nice, a triple sized cache would be awsome. This may be doable at 90nm.

3.
I'm thinking this will come in at 3.5GHz, with legs beyond that. The main reason is the continuous rumors that the 970 tapes out at 2.5 GHz quite often and has hit even higher than that. In fact I suspect that Apple will have 2.5GHz units out around the end of this year or early next year.

Dave




Originally posted by Macrumors
MacEdition's Naked Mole Rat report clarifies some information about the upcoming GPUL2 which was referenced by eWeek as a replacement to the 970 (GPUL) by Mid-2004.

According to MacEdition, the GPUL2 is essentially the same architecture as the PPC 970, and that the Power5 derivative chip is a seperate project. (MacEdition article).


Based on the timing of release, the GPUL2 would presumably be the processor to take Apple to 3GHz by next year. If so, it may cast some doubts on this ambitious report.
Click to expand...
 
Originally posted by Vlade
Will any 970's have level 3 cache, or is that not necessary with a gigahertz bus speed :)
Click to expand...
IBM said last year that the 970 does not support L3 (at least not it the current configuration)
I doubt they will move back to expensive L3 with the amount of memory bandwidth they have.

they will likely bump the L2 up to 1MB when they go to .09 micron though... if they don't the die will begin to get too small to interface with the pinouts.
 
This revision will keep the 970 biting on the heels of the PC world because of it's speed. An increase of L2 to 1024KB should be expected. The die-shrink will also make it cheaper and the bus speed make L3 cache unneeded.

GPUL2 will take the Mac past 3GHZ. I doubt IBM will go beyond 3.25GHZ with it for Apple. Dual 3.25GHZ G5s would be something though, wouldn't it? If Rambus could get their stuff together then they would be a great solution for memory. Biggest problem is their proprietary nature. I would love to see Apple acquire them and make their memory tech propietary to the Mac while allowing other memory manufacturers to make the RAM - but that ain't gonna happen.
 
Originally posted by Mr. MacPhisto
If Rambus could get their stuff together then they would be a great solution for memory. Biggest problem is their proprietary nature. I would love to see Apple acquire them and make their memory tech propietary to the Mac while allowing other memory manufacturers to make the RAM - but that ain't gonna happen.
Click to expand...
well, one problem is the proprietary nature... which manifests as higher prices from the few licensees that make the stuff.
the other problem (aside from cost) is the higher latency.
HT is low latency, I'm not sure the best solution is to use Rambus with a HT driven architecture.

The newest, and upcomming rambus memory is fast, but it is still 16bits wide (usually requiring RIMM pairs to be remotely competitive). It costs twice as much as DDR, and it has higher latency.

Personally I'd rather have dual bank DDR (64bit wide) running 400MHz than dual bank RDRAM (32bit wide) even if it's rambus 1066MHz. Interleaved DDR has enough bandwidth for now at lower latency, and DDR 500 memory is shipping.
DDR is still the way to go. Next year it will be DDR-II so there are still legs under the technology.
Rambus is a nasty company that overblow their importance while attacking other technologies (DDR) with sleazy IP claims and licensing demands. I'd rather have 15% less bandwidth on an open standard than support Rambus
 
on becoming irrelavant

it's interesting, because I am on the threshold of computing power- 2D design, where the computing power is becoming much less important and operating system is more important. At this point, I say "whatever" to raw power and "Do I get a headache with it" to a puchasing decision. Hmmmm, which OS will i choose?
 
Originally posted by Vlade
Will any 970's have level 3 cache, or is that not necessary with a gigahertz bus speed :)
Click to expand...

Apparently with a design like the G5, an L3 cache is totally unnecessary and possibly counterproductive, because it ends up caching more information than is optimal (and introduces another inefficiency).
 
Phil Of Mac:

Apparently with a design like the G5, an L3 cache is totally unnecessary and possibly counterproductive, because it ends up caching more information than is optimal (and introduces another inefficiency).
Click to expand...
Now that is a load of bullcrap. You simply cannot cache too much.

Vlade, ffakr, Phil Of Mac:

High bandwidth and high latency is never a substitute for more chip cache, though it works well for data streaming. The main memory on a G5 is especially high bandwidth and high latency.
 
Originally posted by ddtlm
Phil Of Mac:


Now that is a load of bullcrap. You simply cannot cache too much.

Vlade, ffakr, Phil Of Mac:

High bandwidth and high latency is never a substitute for more chip cache, though it works well for data streaming. The main memory on a G5 is especially high bandwidth and high latency.
Click to expand...

That's not a load of crap.
You can put 8 MB of L3 cache on a G5 processor (if IBM designed it that way) and some things would benefit, but you'd tack on what... an extra $grand$ on a dual proc machine?
Some apps will absolutly NOT benefit from it. Something like RC5 runs just peachy with the much smaller on die caches of existing processors. That's an extreme example, but I'm just trying to make a point here.

I think you are [essentially] trying to make the argument that every Mac would run better with gobs of expensive L3, 8GB of RAM, Striped drives...
Well, yea. But I'm not going to buy a $10,000 workstation.

Also, remember that the dual proc G5s have independent buses. If you take to caching too much data on the independent buses, you run the risk of incurring excessive overhead maintaining cache coherency between CPU busses.

Bottom line,
The G5s have 64bit data paths running at 366 to 400MHz. The expensive L3 cache on the G4 has up to 4GB/s of bandwidth while the memory interface on the dual G5 has 6.4 GB/s of memory bandwidth.
An L3 solution would likely be lower latency, but missed cache hits would increase overall system latency.
Personally, I think we are better off with no L3. It decreases the system complexity, it decreases the system cost, it removes issues related to the L3 cache coherency, and I think the memory subsystem will be sufficient as it stands... especially if you are working on high bandwidth streams of data (larger data sets than a few MB).

jmho
ffakr
 
ffakr:

You can put 8 MB of L3 cache on a G5 processor (if IBM designed it that way) and some things would benefit, but you'd tack on what... an extra $grand$ on a dual proc machine? Some apps will absolutly NOT benefit from it. Something like RC5 runs just peachy with the much smaller on die caches of existing processors. That's an extreme example, but I'm just trying to make a point here.
Click to expand...
Yes but its not a couterpoint to my claims.

I think you are [essentially] trying to make the argument that every Mac would run better with gobs of expensive L3, 8GB of RAM, Striped drives... Well, yea. But I'm not going to buy a $10,000 workstation.
Click to expand...
Quite a lot to conclude from "you cannot cache to much".

An L3 solution would likely be lower latency, but missed cache hits would increase overall system latency.
Click to expand...
Incorrect. The L3 on the G4 stores its tags with the L2 and they are queried in paralell, so a L3 miss imposes no extra latency over an L2 miss.

Also, remember that the dual proc G5s have independent buses. If you take to caching too much data on the independent buses, you run the risk of incurring excessive overhead maintaining cache coherency between CPU busses.
Click to expand...
Two things: one is that you are assuming coherency checks are more detremental than more memory accesses (which I'm not so sure about), and two you are assuming that more cached data means more coherency checks (which I'm not so sure about).

Personally, I think we are better off with no L3. It decreases the system complexity, it decreases the system cost, it removes issues related to the L3 cache coherency, and I think the memory subsystem will be sufficient as it stands... especially if you are working on high bandwidth streams of data (larger data sets than a few MB).
Click to expand...
Yes but the rest of the world that does not work on streams of data will find that chips other than the G5 that have both more cache and lower latency main memory will make compelling performance cases.
 
Phil Of Mac:

You seem to not make the distinction between bandwidth and latency. While the G5 FSB/RAM has lots of bandwidth, it also has high latency, even more than the G4's FSB/RAM. So while the G5 progressed in one area, it regressed in the other. I don't think that the G5 "needs" L3 any less than the G4, but the value of a L3 would have shifted somewhat from bandwidth crutch to latency crutch (although it always serves both roles).

I'm not trying to make any cost/benefit argument here, by the way. I'm sticking strictly to benefit.
 
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