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I am betting

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KingArthur

macrumors regular
Original poster
Jun 15, 2001
236
0
Marion, Ohio
Aparently the guys at apple have found a way to use DDR RAM with the G4 processor on a large scale (not the L3 cache that they have been using). The X-Serve proves this. Now, people are saying that they do not expect the G5 at MWNY, but they do expect major performance improvements. It would be logical to conclude that the next PowerMac will have DDR RAM (which, especially for the graphics people, would improve performance). I personally would expect for the new PowerMac to have these specs:

Up to a 1.4Ghz G4 (Duel 1.2Ghz instead maybe)
2MB per processor of L3 Cache (running at half processor speed)
Support for up to 2GB of DDR RAM (running at twice the bus speed)
133Mhz Bus
Support for Ultra ATA/100 or ATA/133
2-Firewire (Version 2.0 MAYBE)
USB 2.0 Support (MAYBE)Gigabit Ethernet
One of the 3 Graphics cards
And a partredge in a pair tree!
 
Sounds logical, but dont forget DDR=Double Data Rate, so the bus would be 266, right?

Correct me if I am wrong.
 
Originally posted by agreenster
Sounds logical, but dont forget DDR=Double Data Rate, so the bus would be 266, right?

Correct me if I am wrong.
Click to expand...

the bus would remain 133, but since its DDR, the effective bus speed is 266. I believe even those intel 533 FSB machines that have been debuted use a 133 mhz bus, the bigger number is just the effective speed because of the way DDR works.
 
Originally posted by strider42


the bus would remain 133, but since its DDR, the effective bus speed is 266. I believe even those intel 533 FSB machines that have been debuted use a 133 mhz bus, the bigger number is just the effective speed because of the way DDR works.
Click to expand...

Yup, you are 100% correct, P4's still run at 133 MHz technically, the 533 is marketing mostly. It is funny coming from the dark side back to macs, as a lot of PC people who understand low level technology are quite frustrated with what is going on the PC camp as well, especially with some of the crap Intel is doing with chipset support etc. The relable old chipsets with newer names, but basically no real new features, and then charge more for it. all these numbers really do come down to marketing, becauase the way an P4, Athalon, and G4 process are so differnt, it is VERY hard to really see how they differ real life. I think I should go back to being a bike mechanic. there you could just weigh the parts and say, 'wow, thats light' or bomb down a cliff and crash(well maybe not intentionally) and see that the bike is stronger than you are! Anywhoo...
 
Yep... now that Xserve is running on G4's with a 266 System Bus, I would expect the PowerMacs to make that leap too. Look to MWSF for the G5 release (Xserve & PowerMac desktops).

The G4 could make the iBook in San Fran, but that change seems a little less predictable considering what's to come for the TiBooks.
 
Originally posted by tfaz1
Yep... now that Xserve is running on G4's with a 266 System Bus, I would expect the PowerMacs to make that leap too. Look to MWSF for the G5 release (Xserve & PowerMac desktops).

The G4 could make the iBook in San Fran, but that change seems a little less predictable considering what's to come for the TiBooks.
Click to expand...

Well, if Apple can continue to milk the G4 for a little while longer, there's no real reason to believe now, with the new mobo and all coming along to give it a big boost in performance, that we won't see the G5 until later in 03. If you coud get a 2MHz G4, that would be an impressive thing in its own right. And imagine a dual...

Just a thought.:D
 
Originally posted by dukestreet


If you coud get a 2MHz G4, that would be an impressive thing in its own right. And imagine a dual...

Just a thought.:D
Click to expand...

Wow, a 2Mhz dual. That would be like having a 4Mhz computer. Someday I hope to have a computer that could run that fast.:D
 
Originally posted by macstudent


Wow, a 2Mhz dual. That would be like having a 4Mhz computer. Someday I hope to have a computer that could run that fast.:D
Click to expand...

Easy, big guy. Go back to around 1980 for that type of material.

With all of this argument of DDRAM and a new enclousure, I think some of us are forgetting other possibilities. What if Apple uses a much faster graphics card, a larger L3 cache, or room for 4GB of RAM? What if Apple releases a DVD-RW at extremely fast speeds, three-digit GB Hard Drives, or chips that use even less power than the current Apollo chips? Maybe Apple is going to update their commonly accessable and used external hardware, such as a new keyboard or a new mouse, or maybe Apple will add Bluetooth to their line of products.

Those are just a few suggestions. But I think some of us are forgetting about some rather important issues. But I would agree on faster G4s, with some sort of dual peak, and maybe DDRAM. I would also like to guess that the following Macs may have a faster Superdrive, but you never know.
 
To clarify things with the DDR RAM...

The Intel machines use a 133 Mhz system bus. That is the speed that the computer can send data from or to the hard disk, USB, Firewire, Ethernet, and PCI Cards to or from the RAM. Basically all things must enter the RAM (except the graphics card and SOME other direct access components) and there the RAM has a 266 Mhz bus to the Front side of the processor (the trace cache). Now, the trace cache doubles that and does an effective 533Mhz cycle to the processor itself. The thing is, well, you only access the majority of the components at a louzy 133Mhz speed. I am not 100% sure this is the exact means, but you get the general gist.

I doubt that Apple would boost the actual bus speed until the G5, because the G4 at this time does not support a faster bus speed (I think). Now, the resources spent on developing DDR support are obvious. When the G5 comes out, what processors will the iMacs use?????? The G4 of course! So this makes perfect sense that the average Joe would still need a faster RAM bus (especially since the average Joe mostly wants the computer for gaming and the OS).

As I said before, I believe that Apple is planning on making good strides with the PowerMac G4 before the G5 is released; this gives them time to make a pretty penny off of all the new technology they added to the machine. And, Hey!, who knows, Apple may not even add any of this to the computer or it may add other things, but in reality, the G4 needs to stay alive for the iMac and have some major improvements. What better to release the technology on than the highest priced machine so that they can make an even better profit?
 
King Arthur:

Thanks for that explanation--I've been trying to learn more about the PC's bus architecture for a while, and frankly don't understand the "quad pumping" stuff. Do you know any reference web pages to explain more on the true speed and performance of those buses? Thanks.


Tokyo
 
Try this

Arstechnica.com is a wonderful place to begin learning about the hardware. Just go there and click on the "CPU Theory" link to the left of the screen and enjoy!
 
XServe

XServe doesn't use a 266 mhz bus it uses a 133mhz bus. It is on apple's website. Don't expect a faster bus at MWNY unless the G5's are realeased.
 
It's funny, how the marketing hype on the Wintel side always gets out of hand. The PC people alway say how far ahead of us poor Mac folk in the high-MHz bus race.

Yet when you look for memory you're still finding that the majority of the stuff on the shelves is still PC-133, DDR-266, or the Rambus stuff.

Sort of makes one wonder what they're talking about when they say they're computer has a 400/533-Mhz bus and they're still using DDR-266 memory. And laughing at our slow 100 & 133 MHz buses on the Macs.
 
Did I say that the XServe uses a 266Mhz bus? no. I said that the XServe uses a 266Mhz (effective) RAM Bus. This RAM bus speed is not actually a 266Mhz bus, but a 133Mhz bus that can handle 2 pieces of data at once (double pumped). This gives the appearance of a 266Mhz bus speed from the DDR RAM to the Processor. The rest of the components can send their data to the RAM at a 133Mhz SYSTEM BUS speed.

Tokyo:
The method of Quad-pumping is basically this:
In order for the processor to interpret the each sigal as a one or a zero, there has to be a very, very short pause between each signal (basically so that the processor can tell where a signal begins and ends).

Now, what double-pumping/quad-pumping does is:
Roughly double or quadruple the number of transisters are squeezed between the processor and the RAM/cache. Since the pause between signals is measured in number of transisters, you are able to fire a second piece of data after the first one has cleared a certin number of transisters. So if we are quad pumping a bus, we are able to fire a second signal after the first signal has traveled 1/4 of the way to the processor. Thus, in one processor cycle, you have fired 4 signals instead of one. 133Mhz times 4 is an effective 533Mhz

The thing is:
If you are accessing the HD or other component of the computer, the RAM is only recieving one signal per cycle. Now, the RAM speed to the processor is down to the origional 133Mhz where it will remain as long as the next needed signal is from that component. The AGP 4x is a quad-pumped bus so that the graphics card can recieve and send data at a faster pace. A PCI card only communicates with the RAM at a 33Mhz or 66Mhz bus speed, and therefore accessing PCI cards is 1/4 to 1/2 the bus speed which makes it 1/8 ti 1/4 the 533Mhz speed that Intel is boasting. Remember, Intel only tells you the speed of its components under ideal conditions.

One last thing:
DDR RAM stands for DOUBLE Data Rate RAM. This means that the RAM is double-pumped. The only thing that is QUAD-pumped is the trace cache (L1 and L2 caches). Therefore, if the processor is recieving signals from the cache only, it is effectively 533Mhz, if it is recieving signals from the RAM, it is effectively 266Mhz, and if it is recieving it from almost anywhere else, it is only a maximum or 133Mhz.

I hope I have not completely confused you. I should have drawn a diagram and posted it online, but I have to get to sleep now. So goodnight.
 
Originally posted by KingArthur
I hope I have not completely confused you. I should have drawn a diagram and posted it online, but I have to get to sleep now. So goodnight.
Click to expand...
Quite the contrary, my friend. Thank you very much--I was able to follow most of it, hopefully all. It sounds like the pumping technique is somewhat similar to pipelining--i.e., an assembly-line approach, as opposed to a one-bucket bucket brigade.

As for the drawbacks, it sounds like the bottleneck is simply pushed back from the Ram/cache-CPU bus to the other buses in the system; the process is only helpful if the stream of data from RAM or cache is not dependent on outside data. But do I understand correctly in that the RAM never sends data to the processor at 4x speed, but rather only at double (i.e., 266MHz)? Only the cache enjoys the quad pumping? Because I thought that the L3 (off-chip) cache had an independent high-speed bus to the CPU, running at 1/2 or 1/4 of the processor speed. Maybe that's where I'm confused.

Nevertheless, it is now far more clear than it was before; I thank you much for information I was not able to find elsewhere after a pretty long search. My gratitude.


Tokyo
 
The P4 front side bus on the intel side was designed most likely have a high speed/bandwidth path between memory and the CPU, but was Rambus only. And the Rambus never quite lived up the claims when tested against more convential sdram, and nobody liked the $'s in patent tolls needed to produce it anyway.

http://program.intel.com/shared/products/chipsets/850/images/850family_diag_sm.gif

The DDR-266 version of the P4 chipset means that the P4s chipset I/O bandwidth is the same as the XServe. And thus both the PPC and P4 are limited to 2.1GB/s between memory and the CPU using DDR-266.

http://program.intel.com/shared/products/chipsets/845e/images/845e_diag_340px.gif

So we are really bandwidth limited and not clock speed limited when compared to the PC world, since we know that the PPCs are fast enough to starve the caches at the current MHz level. At least until Apple brings out the next generation motherboard architecture.
 
AFAIK...

...the Pentium 4 actually has a dual channel 133MHz DDR bus. So it's like two DDR 133 buses that are out of sync with each other so that they act like a DDR 266 bus (533 effective speed). The trace cache has nothing to do with the bus, it's simply an innovative way of using the level 1 cache to get around the limitations of x86. The P4's huge amount of memory bandwidth and it's large level 2 cache are the only reasons it can keep up with the AthlonXP. If you look at the benchmarks, the P4 almost always loses, the P4A just about ties (double level 2 cache), and the new 533 bus P4As tend to beat the AthlonXP. Either of them will beat the current G4s at almost all tasks (slow memory, small level 1 and 2 caches, low clockspeed. Its only advantages are Altivec, the level 3 cache, and being PowerPC. I think faster memory will even the playing field a lot).
 
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