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IBM's new "dual stress liner" technique: good for the G5?

D

dolphin842

macrumors 65816
Original poster
Jul 14, 2004
1,172
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I came across an article on various tech sites today about IBM touting its new "dual stress liner" technique:

IBM and AMD have found a way to improve transistor performance by up to 24 per cent - without increasing the power draw - using a tweaked implementation of Big Blue's 'strained silicon' process.
[...]
IBM will ship a variety of 90nm Power and PowerPC chips using the technique in the H1 2005 timeframe.
Click to expand...
It looks as if IBM is keeping the window of delivery for these chips open (like Apple is for Tiger) in case they run into new problems... but there nevertheless appears to be a good future for the G5.

Any thoughts? Shall we start another 'imminent PowerBook G5' thread? ;)

Here's a link to the most detailed article I saw.
 
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