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Axemantitan

macrumors 6502a
Original poster
Mar 16, 2008
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At an ISSCC session Monday, Intel went into new detail on its forthcoming 8-core, 16-thread Xeon processor, a 64-bit processor that's a member of the Nehalem family. Much of the session was focused on the packaging and power aspects of the device, so I'll recap some of the more interesting parts of that here.

The Intel presenter explained that the Xeon has three different clock and voltage domains: the core region, the uncore region, and the I/O region. (You may recall from previous coverage of Nehalem that the "uncore" region of the processor is so named because it's the area that doesn't have a processor core in it; this area is mostly cache.)

These separate clock and voltage domains are used for power management, and the isolation that they provide also aids Intel in implementing "Turbo Mode." Turbo mode is Intel's name for its technology that lets it shut down one or more cores in order to focus the chip's power budget on the cores that are actually active (i.e., by increasing the voltage and clockspeed of the active cores). The cores' variable voltage ranges from 0.85V to 1.1V, while the voltages and clocks of the uncore and I/O domains are fixed.

http://arstechnica.com/hardware/news/2009/02/intel-details-eight-core-xeon-cache-and-core-recovery.ars
 
anybody know if that will reduce performance compared to other 2/4/6-core processors that aren't simply broken larger chips with disabled cores... ones that were intentionally made to be 2 or 4 or 6 -core chips?
 
So they're going to make a bunch of Beckton and sell some of the defects as two and four core Gainestown?

Great. :(

It's inevitable parts will be produced that are partially defective. Moore's Law dictates that as the complexity increases, so will the defect rate. If they're thrown away, the cost is passed on to the remaining units (fully functional), increasing the per unit cost on those that can be shipped.

This is a way of recycling that could help in the end. It even has the potential of creating a niche market of lower cost servers/workstations that are built on these "remanufactured" components.
 
anybody know if that will reduce performance compared to other 2/4/6-core processors that aren't simply broken larger chips with disabled cores... ones that were intentionally made to be 2 or 4 or 6 -core chips?

Nah. This is a pretty standard way of doing things. They also include a bit of extra cache so they can disable any defective bits and still meet the target amount.
 
It's inevitable parts will be produced that are partially defective. Moore's Law dictates that as the complexity increases, so will the defect rate. If they're thrown away, the cost is passed on to the remaining units (fully functional), increasing the per unit cost on those that can be shipped.

This is a way of recycling that could help in the end. It even has the potential of creating a niche market of lower cost servers/workstations that are built on these "remanufactured" components.

To expand on this, there is absolutely nothing wrong with these chips. Another more well known example would be the Cell, which is manufactured with 9 cores even though only 8 are enabled. Redundancy is good, especially if there is no difference on the end users, er, end.
 
To expand on this, there is absolutely nothing wrong with these chips. Another more well known example would be the Cell, which is manufactured with 9 cores even though only 8 are enabled. Redundancy is good, especially if there is no difference on the end users, er, end.
True. :D I should have elaborated. ;)

Not redundancy in this case, but the operational cores will work affectively. As good as those in parts that didn't go through "surgery". :) The only thing that might get confusing, is the additional part numbers (if they do this). ;)

Proper server/workstation parts at a decent discount?
Bring 'em on Intel. :D
 
Not redundancy for us, but redundancy for Intel. Two of the cores are allowed to not work and they still have a product.
 
Not redundancy for us, but redundancy for Intel. Two of the cores are allowed to not work and they still have a product.
Ahh...

It might seem odd (intentionally using more wafer area), but given the complexity of current parts, and the exponential increase, this method may become common I guess. One way to improve the odds of a part being able to work as intended. :)
 
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