At an ISSCC session Monday, Intel went into new detail on its forthcoming 8-core, 16-thread Xeon processor, a 64-bit processor that's a member of the Nehalem family. Much of the session was focused on the packaging and power aspects of the device, so I'll recap some of the more interesting parts of that here.
The Intel presenter explained that the Xeon has three different clock and voltage domains: the core region, the uncore region, and the I/O region. (You may recall from previous coverage of Nehalem that the "uncore" region of the processor is so named because it's the area that doesn't have a processor core in it; this area is mostly cache.)
These separate clock and voltage domains are used for power management, and the isolation that they provide also aids Intel in implementing "Turbo Mode." Turbo mode is Intel's name for its technology that lets it shut down one or more cores in order to focus the chip's power budget on the cores that are actually active (i.e., by increasing the voltage and clockspeed of the active cores). The cores' variable voltage ranges from 0.85V to 1.1V, while the voltages and clocks of the uncore and I/O domains are fixed.
http://arstechnica.com/hardware/news/2009/02/intel-details-eight-core-xeon-cache-and-core-recovery.ars