Overclock iMac G5

[topgunn]

From August 31, 2004 when the iMac G5 was first introduced, many assumed that the CPU was underclocked to prevent the mid-range iMac from competing too much with the G5 PowerMacs. At that time, Apple posted an uncompressed image of the iMac's innards posted on Apple's PR page. There were four resistors clearly marked as CPU CLK and NB CLK which quite possibly control the clock multiplier and FSB speed. There was a lot of speculation for a few weeks but I haven't heard anything else about this since then.

I am curious to see if these jumpers in fact control the clock multiplier and FSB. On my 1.6GHz iMac G5, both CPU CLK locations are occupied while the two NB CLK pads are unoccupied. I would appreciate it if someone with a 1.8GHz iMac G5 would be kind enough to post what the configuration is on their machine. As I said above, they are clearly labeled and are located just to the left of the heatsink and just right of the center of the board.

So again, if one of you iMac G5 owners with a 1.8GHz CPU would be so kind as to post the configuration of said jumpers, I would appreciate it. Hopefully they will be different thus lending credence to this speculation.

Thanks in advance.

 

[frescies]

From August 31, 2004 when the iMac G5 was first introduced, many assumed that the CPU was underclocked to prevent the mid-range iMac from competing too much with the G5 PowerMacs. At that time, Apple posted an uncompressed image of the iMac's innards posted on Apple's PR page. There were four resistors clearly marked as CPU CLK and NB CLK which quite possibly control the clock multiplier and FSB speed. There was a lot of speculation for a few weeks but I haven't heard anything else about this since then.

I am curious to see if these jumpers in fact control the clock multiplier and FSB. On my 1.6GHz iMac G5, both CPU CLK locations are occupied while the two NB CLK pads are unoccupied. I would appreciate it if someone with a 1.8GHz iMac G5 would be kind enough to post what the configuration is on their machine. As I said above, they are clearly labeled and are located just to the left of the heatsink and just right of the center of the board.

So again, if one of you iMac G5 owners with a 1.8GHz CPU would be so kind as to post the configuration of said jumpers, I would appreciate it. Hopefully they will be different thus lending credence to this speculation.

Thanks in advance.

I will! But not tonight... I'm beat and I NNEEEEED sleep. Let me get back to you tomorrow if no-one else does

 

[sorryiwasdreami]

I've got a 1.8Ghz iMac G5. I'll see what I can find.

 

[topgunn]

Thanks, guys. If I am guessing right, there will be a difference on the NB CLK while the CPU CLK should be the same since both versions have a 3x multiplier.

 

[topgunn]

Anyone had a chance to take a look at this yet?

 

[Sun Baked]

There is a chance the Support Processor is in the U3-Lite, of course they could still be using a HC08 or PPC405.

If you have no idea what I'm talking about, then the chances of you overclocking the machine are nil.

Also an outside chance that the SMU is functioning as both the Support Processor and the SMU.

---

But it's a little more than just jumpers, since you also need to program in the skew values for the e-Bus.

 

[topgunn]

There is a chance the Support Processor is in the U3-Lite, of course they could still be using a HC08 or PPC405.

If you have no idea what I'm talking about, then the chances of you overclocking the machine are nil.

Also an outside chance that the SMU is functioning as both the Support Processor and the SMU.

---

But it's a little more than just jumpers, since you also need to program in the skew values for the e-Bus.

Thank you for your input. So, do you have a 1.8GHz iMac? If so, would you mind checking the state of the resistors for me?

Thanks

 

[Sun Baked]

Thank you for your input. So, do you have a 1.8GHz iMac? If so, would you mind checking the state of the resistors for me?

Thanks

I see you still don't get it, the G5 bus speed isn't controlled by resistors it's controlled by the Service Processor and the Memory Controller.

With the Service Processor setting the initial clock speeds and bringing the system up to stable clocks after a POR. And this also include determining skew values for the FSB, which change with clock speed.