Possible solutions for my dual 5k monitors

adogwithacat · Mar 23, 2022

1st Monitor: Studio Display(Latest info is it shoud be DP 1.2, DSC supported)
2nd Monitor：a 5K monitor assembled by an unknown small company(one Thunderbolt 3 port, one DP 1.4 port, no DSC)

Both of them are on the way... But I can think first...

I think my Macbook should be fine with them. The problem is about my PC, which is ROG Z690-I(two usb-c ports which support Thuderbolt 4), 12900K, Intel UHD 770(integrated graphics）. Yes, there're two ports on the motherboard, but only one Thunderbolt controller. I'm not sure the bandwidth of thunderbolt is enough for two monitors.

Solution 1：Just use two thunderbolt ports for two monitors.
According to current information,
Data rate of the 1st monitor: 22.18Gbps / 2(since DSC) = 11Gbps, --------> 3 lanes of DP should be enough
Data rate of the 2st monitor: 22.18Gbps, --------> 5 lanes of DP should be enough
It seeems that the bandwidth is enough. But I don't know, can DP lanes distributed like this? Does this solution really work?

Solution 2: One usb-c port(in Thunderbolt 3 mode) for the 1st monitor, the other usb-c port(in DP only mode) for the 2nd monitor.
The question is, if one usb-c port is in DP only mode, does it still occupy the bandwidth of it thunderbolt controller, cause the other usb-c port in Thunderbolt mode doesn't have enough bandwidth?

Solution 3: Buy a graphic card for the 2nd monitor
Since the 2nd monitor has a DP 1.4 port, leave thunderbolt to the 1st monitor.

Any ideas?

velocityg4 · Mar 23, 2022

You can try it. But I don't think it'll do both. From what I can tell from the three Intel Thunderbolt 4 chipsets. Is they just do one DP 1.4 connection. Which is limited to one 5K @60hz connection.

I'd go with solution 3. I'd also expect any card which can run the one Display will have multiple DP connections or HDMI 2.0 connections. It'll also be way faster than integrated graphics. So, I'd just use that for both displays. Getting back the RAM the integrated graphics uses.

Amethyst1 · Mar 23, 2022

velocityg4 said:
From what I can tell from the three Intel Thunderbolt 4 chipsets. Is they just do one DP 1.4 connection. Which is limited to one 5K @60hz connection.

Thunderbolt 4 requires that two DisplayPort connections be fed into the Thunderbolt controller. This is optional with Thunderbolt 3; Macs are guaranteed to be wired up that way though.

5K60 can be done using just a HBR2 link rate if DSC is used: this is one way the Studio Display does it. So if both screens supported DSC it would definitely work because two HBR2 connections are possible via one Thunderbolt 3/4 controller. In the OP's case, one screen needs a HBR3 connection for 5K60 because it doesn't support DSC. I'm not sure if HBR2+HBR3 is possible via one Thunderbolt 3/4 controller.
@joevt will know the answer

velocityg4 said:
I'd also expect any card which can run the one Display will have multiple DP connections or HDMI 2.0 connections.

HDMI 2.0 is no good for 5K; HDMI 2.1 is required for that. In any case, the OP needs two DisplayPort 1.4 outputs (one as a USB-C port or with a suitable adapter/cable) along with DSC support.

joevt · Mar 23, 2022

5120x2880 60Hz uses a pixel clock ≈924.15 MHz (CVT-RB2). Studio Display default timing is 936MHz. Some 5K displays might use 967MHz.

At DSC@12bpp, the Studio Display requires 11.23 Gbps.
A 967MHz display at 8bpc requires 23.2 Gbps.

HBR3 max is 25.92 Gbps.
HBR2 max is 17.28 Gbps.
Thunderbolt 3/4 is 40 Gbps.

While 11+23 < 40 Gbps, The Thunderbolt driver software will not allow both a HBR2 and HBR3 connection to exist on the same Thunderbolt cable (although it would be possible for it to force that mode - but such software to do that doesn't exist except in macOS for the XDR display which uses two HBR3 connections over a single Thunderbolt cable).

Therefore, you must use two different Thunderbolt ports.

But if you really only want to use one Thunderbolt port: for the HBR3 display, you could try 6bpc or a lower refresh rate such as 45Hz to get under the HBR2 max. But you would first have to connect the Studio Display, then connect the other display afterward. If you connect the HBR3 display first, then the Studio Display would only be able to connect at HBR link rate. If Studio Display tries to take two DisplayPort connections (for dual tile mode) then you need a method to force a single DisplayPort connection (such as using a USB-C cable instead of a Thunderbolt cable).

FYI, DisplayPort support 1, 2 or 4 lane connections at RBR, HBR, HBR2, & HBR3 link rates.

But wait. You are using a PC running Windows? Windows supports MST. Use a DisplayPort 1.4 MST hub to more efficiently divide the DisplayPort bandwidth. Both displays can be connected to a single MST hub. The MST hub has a max input of 25.92 Gbps, but the input can use DSC. The MST hub can decompress the DSC stream for the HBR3 display that does not support DSC. The HP Thunderbolt Dock G2 is a Thunderbolt 3 dock that contains an MST hub. The dock's MST hub has a USB-C port that supports DisplayPort Alt Mode, so it should work with the Studio Display. The MST hub also has two DisplayPort 1.4 ports. You could also try a normal DisplayPort 1.4 MST hub, and use a Belkin Charge and Sync Cable for the USB-C display.

adogwithacat · Mar 23, 2022

joevt said:
5120x2880 60Hz uses a pixel clock ≈924.15 MHz (CVT-RB2). Studio Display default timing is 936MHz. Some 5K displays might use 967MHz.

At DSC@12bpp, the Studio Display requires 11.23 Gbps.
A 967MHz display at 8bpc requires 23.2 Gbps.

HBR3 max is 25.92 Gbps.
HBR2 max is 17.28 Gbps.
Thunderbolt 3/4 is 40 Gbps.

While 11+23 < 40 Gbps, The Thunderbolt driver software will not allow both a HBR2 and HBR3 connection to exist on the same Thunderbolt cable (although it would be possible for it to force that mode - but such software to do that doesn't exist except in macOS for the XDR display which uses two HBR3 connections over a single Thunderbolt cable).

Therefore, you must use two different Thunderbolt ports.

But if you really only want to use one Thunderbolt port: for the HBR3 display, you could try 6bpc or a lower refresh rate such as 45Hz to get under the HBR2 max. But you would first have to connect the Studio Display, then connect the other display afterward. If you connect the HBR3 display first, then the Studio Display would only be able to connect at HBR link rate. If Studio Display tries to take two DisplayPort connections (for dual tile mode) then you need a method to force a single DisplayPort connection (such as using a USB-C cable instead of a Thunderbolt cable).

FYI, DisplayPort support 1, 2 or 4 lane connections at RBR, HBR, HBR2, & HBR3 link rates.

But wait. You are using a PC running Windows? Windows supports MST. Use a DisplayPort 1.4 MST hub to more efficiently divide the DisplayPort bandwidth. Both displays can be connected to a single MST hub. The MST hub has a max input of 25.92 Gbps, but the input can use DSC. The MST hub can decompress the DSC stream for the HBR3 display that does not support DSC. The HP Thunderbolt Dock G2 is a Thunderbolt 3 dock that contains an MST hub. The dock's MST hub has a USB-C port that supports DisplayPort Alt Mode, so it should work with the Studio Display. The MST hub also has two DisplayPort 1.4 ports. You could also try a normal DisplayPort 1.4 MST hub, and use a Belkin Charge and Sync Cable for the USB-C display.

Yes. The PC is running Windows. It's good to know the MST hub is capable of decompressing the DSC stream. Actually I noticed there're several MST hubs which support DSC, but I just don't know how they support.

joevt · Mar 23, 2022

adogwithacat said:
Yes. The PC is running Windows. It's good to know the MST hub is capable of decompressing the DSC stream. Actually I noticed there're several MST hubs which support DSC, but I just don't know how they support.

I don't know if an MST hub can do two 5K displays.

I have successfully done one 5K display (it's actually dual tile: 483.25MHz per tile = 23 Gbps at 8bpc)
I have successfully done three 4K 533MHz 8bpc displays. That's 38.3 Gbps.

Two 5K 936 MHz 8bpc displays is 44.9 Gbps. Maybe that's not too much. Or maybe it helps that one uses DSC pass thru.

DSC@12bpp can do up to 2160 MHz (HBR3 x4) but there's some overhead unaccounted for in that (3% for FEC. More for MST).
DSC@8bpp can do up to 3240 MHz but you don't get to choose the bpp (except macOS has a preference for changing that which I haven't seen anyone try yet).
https://forums.macrumors.com/thread...-on-mac-pro-yes-you-can.2309750/post-30748427

You have to look at the DPCD registers of the MST hub to see the exact DSC capabilities. AGDCDiagnose in macOS can do that. I added a similar capability in my macOS AllRez utility (I think mine might be easier to read?). I want to find a method to read the DPCD registers of all DisplayPort devices in a DisplayPort tree (you can connect multiple MST hubs together, for example, and some HDMI adapters are actually MST hubs).
https://forums.macrumors.com/thread...-on-mac-pro-yes-you-can.2309750/post-30760662

The DisplayPort 1.4 spec is not available for download so I don't know what all the DPCD registers mean regarding DSC.

Below is sample output from my AllRez command for the MST hub in my HP Thunderbolt Dock G2 connected to an unflashed GC-ALPINE RIDGE in my MacPro3,1 using DisplayPort 1.2 from a EVGA Nvidia GeForce GTX 680.

The BRANCH_OUI and BRANCH_ID show that this is a Synaptics VMM-5333 MST hub.
https://www.synaptics.com/products/video-interface-ics
https://uploadcdn.oneyac.com/attachments/userfile/b4/13/1593672494627_4765.pdf

Actually, I have 3 other MST hubs connected to that MST hub before the display connection but I haven't found a method to read the DPCD from the other devices in the chain yet.

Code:

                DisplayPort = {
                    00000h: 12 14 c4 81 01 11 01 83 2a 3f 04 00 00 00 02 00  ........*?......
                    00020h: 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00060h: 01 21 00 14 0b 00 00 00 01 03 02 11 08 00 00 04  .!..............
                    00080h: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00090h: 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    000a0h: 09 1e 10 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00100h: 14 84 00 00 00 00 00 10 7b 00 00 00 00 00 00 00  ........{.......
                    001c0h: 00 00 3f 00 00 00 00 00 00 00 00 00 00 00 00 00  ..?.............
                    00200h: 01 00 77 77 01 03 22 22 00 00 00 00 00 00 00 00  ..ww..""........
                    00210h: 00 80 00 80 00 80 00 80 00 00 00 00 00 00 00 00  ................
                    00240h: ec fc bc 51 9d 3d 00 00 00 00 00 00 00 00 00 00  ...Q.=..........
                    00280h: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    002c0h: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    004a0h: 54 45 53 4c 41 03 01 10 00 00 00 00 00 00 00 00  TESLA...........
                    004b0h: 94 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00500h: 90 cc 24 53 59 4e 41 53 33 10 05 04 05 00 00 00  ..$SYNAS3.......
                    00560h: 00 01 01 02 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    01400h: 10 14 c9 a0 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    01410h: 00 00 00 00 03 00 87 00 00 00 00 00 00 00 00 00  ................
                    02000h: 00 00 01 00 00 00 00 00 00 00 00 00 77 77 01 03  ............ww..
                    02200h: 14 14 c4 81 01 11 01 83 2a 3f 04 00 00 00 84 00  ........*?......
                    02210h: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    68000h: d9 c8 cd 9c 4a b4 6d 00 00 00 00 00 00 00 00 00  ....J.m.........
                    68020h: 00 00 00 00 00 00 00 00 03 00 01 01 00 00 00 00  ................

                    Receiver Capability
                        00000h DPCD_REV: 1.2
                        00001h MAX_LINK_RATE: HBR2
                        00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                        00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                        00004h NORP: 2
                        00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                        00007h DOWN_STREAM_PORT_COUNT: 3, OUI_SUPPORT
                        00008h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT, ?0x28
                        00009h RECEIVE_PORT_0_BUFFER_SIZE: 2048 bytes per lane
                        0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                        0000eh TRAINING_AUX_RD_INTERVAL: 8ms all
                        00021h MSTM_CAP: MST_CAP
                        00022h NUMBER_OF_AUDIO_ENDPOINTS: 1
                        00060h DSC_SUPPORT: DSC_DECOMPRESSION_IS_SUPPORTED
                        00061h DSC_REV: 1.2
                        00062h DSC_RC_BUF_BLK_SIZE: 1kB
                        00063h DSC_RC_BUF_SIZE: 20 * DSC_RC_BUF_BLK_SIZE
                        00064h DSC_SLICE_CAP_1 & 2: 1, 2, 4 max slices per DisplayPort DSC sink
                        00067h DSC_MAX_BITS_PER_PIXEL: 16 bpp
                        00069h DSC_DEC_COLOR_FORMAT_CAP: RGB, YCbCr 4:4:4
                        0006ah DSC_DEC_COLOR_DEPTH_CAP: 8 bpc
                        0006bh DSC_PEAK_THROUGHPUT: MODE_0 = 340 Mp/s, MODE_1 = 340 Mp/s
                        0006ch DSC_MAX_SLICE_WIDTH: 2560 pixels
                        0006fh DSC_BITS_PER_PIXEL_INC: 1 bpp
                        00080h DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort, HPD aware
                        00090h FEC_CAPABILITY: FEC_CAPABLE, FEC_UNCORR_BLK_ERROR_COUNT_CAP, FEC_CORR_BLK_ERROR_COUNT_CAP, FEC_BIT_ERROR_COUNT_CAP
                        000a0h DSC_BRANCH_OVERALL_THROUGHPUT_0: 1050 Mp/s
                        000a1h DSC_BRANCH_OVERALL_THROUGHPUT_1: 2100 Mp/s
                        000a2h DSC_BRANCH_MAX_LINE_WIDTH: 5120 pixels
                    Link Configuration
                        00100h LINK_BW_SET: HBR2
                        00101h LANE_COUNT_SET: 4, ENHANCED_FRAME_EN
                        00107h DOWNSPREAD_CTRL: SPREAD_AMP_0_5
                        00108h MAIN_LINK_CHANNEL_CODING_SET: SET_ANSI_8B10B, SET_ANSI_128B132B, ?0x78
                        001c2h PAYLOAD_ALLOCATE_TIME_SLOT_COUNT: Time Slot Count of VC Payload Id in DPCD address 2C0h = 63
                    Link/Sink Device Status
                        00200h SINK_COUNT: 1
                        00202h LANE0_1_STATUS: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00202h LANE0_1_STATUS: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00203h LANE2_3_STATUS: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00203h LANE2_3_STATUS: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00204h LANE_ALIGN_STATUS_UPDATED: INTERLANE_ALIGN_DONE
                        00205h SINK_STATUS: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                        00206h ADJUST_REQUEST_LANE0_1: LANE0 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00206h ADJUST_REQUEST_LANE0_1: LANE1 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00207h ADJUST_REQUEST_LANE2_3: LANE2 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00207h ADJUST_REQUEST_LANE2_3: LANE3 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00210h SYMBOL_ERROR_COUNT_LANE0: 0, valid
                        00212h SYMBOL_ERROR_COUNT_LANE1: 0, valid
                        00214h SYMBOL_ERROR_COUNT_LANE2: 0, valid
                        00216h SYMBOL_ERROR_COUNT_LANE3: 0, valid
                        00240h TEST_CRC_R_CR: 0xfcec
                        00242h TEST_CRC_G_Y: 0x51bc
                        00244h TEST_CRC_B_CB: 0x3d9d
                        00282h FAUX_BACK_CHANNEL_SYMBOL_ERROR_COUNT_CONTROL: COUNT_SYMBOL
                        002c0h PAYLOAD_TABLE_UPDATE_STATUS: PAYLOAD_TABLE_UPDATED, PAYLOAD_ACT_HANDLED
                    Sink Device-Specific
                        004a0h : 54 45 53 4c 41 03 01 10 00 00 00 00 00 00 00 00  TESLA...........
                        004b0h : 94 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    Branch Device-Specific
                        00500h BRANCH_OUI: 90-CC-24 = Synaptics, Inc
                        00503h BRANCH_ID: 53 59 4e 41 53 33  SYNAS3
                        00509h BRANCH_HW_REV: 1.0
                        0050ah BRANCH_SW_REV: 5.4
                        0050ch : 05 00 00 00  ....
                        00560h : 00 01 01 02 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    Sink Control
                        00600h SET_POWER: SET_POWER_D0
                    Sideband MSG Buffers
                        01400h SIDEBAND_MSG_DOWN_REP: 10 14 c9 a0 00 00 00 00 00 00 00 00 00 00 00 00  ................
                        01410h : 00 00 00 00 03 00 87 00 00 00 00 00 00 00 00 00  ................
                    DPRX ESI (Event Status Indicator)
                        02002h SINK_COUNT_ESI: 1
                        0200ch LANE0_1_STATUS_ESI: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200ch LANE0_1_STATUS_ESI: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200dh LANE2_3_STATUS_ESI: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200dh LANE2_3_STATUS_ESI: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200eh LANE_ALIGN_STATUS_UPDATED_ESI: INTERLANE_ALIGN_DONE
                        0200fh SINK_STATUS_ESI: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                    Extended Receiver Capability
                        02200h DP13_DPCD_REV: 1.4
                        02201h MAX_LINK_RATE: HBR2
                        02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                        02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                        02204h NORP: 2
                        02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                        02207h DOWN_STREAM_PORT_COUNT: 3, OUI_SUPPORT
                        02208h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT, ?0x28
                        02209h RECEIVE_PORT_0_BUFFER_SIZE: 2048 bytes per lane
                        0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                        0220eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                        02210h DPRX_FEATURE_ENUMERATION_LIST: VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED, VSC_EXT_VESA_SDP_SUPPORTED, VSC_EXT_VESA_SDP_CHAINING_SUPPORTED, VSC_EXT_CEA_SDP_SUPPORTED, VSC_EXT_CEA_SDP_CHAINING_SUPPORTED
                    HDCP 1.3 and HDCP 2.2
                        68000h AUX_HDCP_BKSV: d9 c8 cd 9c 4a  ....J
                        68005h AUX_HDCP_RI_PRIME: b4 6d  .m
                        68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE, BCAPS_REPEATER_PRESENT
                        6802ah AUX_HDCP_BINFO: DEVICE_COUNT = 1, DEPTH = 1
                }; // DisplayPort

Looking at the DSC related registers, we see the following:

00060h DSC_SUPPORT: DSC_DECOMPRESSION_IS_SUPPORTED decompression from the MST hub is supported
00061h DSC_REV: 1.2 1.2 is the latest (or 1.2a?)
00062h DSC_RC_BUF_BLK_SIZE: 1kB ?
00063h DSC_RC_BUF_SIZE: 20 * DSC_RC_BUF_BLK_SIZE 20 kB
00064h DSC_SLICE_CAP_1 & 2: 1, 2, 4 max slices per DisplayPort DSC sink 4 slices is good, 3 possible DisplayPort sinks, 12 slices total?
00067h DSC_MAX_BITS_PER_PIXEL: 16 bpp macOS only uses 12 bpp for DSC.
00069h DSC_DEC_COLOR_FORMAT_CAP: RGB, YCbCr 4:4:4 RGB or 4:4:4 are best color formats (4:2:0 and 4:2:2 would add additional compression but 8bpp would be preferable).
0006ah DSC_DEC_COLOR_DEPTH_CAP: 8 bpc no 10bpc? that's not good. hope it doesn't matter.
0006bh DSC_PEAK_THROUGHPUT: MODE_0 = 340 Mp/s, MODE_1 = 340 Mp/s 340 MHz * 4 slices = 1360 MHz. I guess that's good enough for 5K.
0006ch DSC_MAX_SLICE_WIDTH: 2560 pixels 2560 * 4 slices = 10K. More than what we need.
0006fh DSC_BITS_PER_PIXEL_INC: 1 bpp This means 8,9,10,11,12,13,14,15,16bpp are supported?
00080h DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort, HPD aware hot plug detect.

00090h FEC_CAPABILITY: FEC_CAPABLE, FEC_UNCORR_BLK_ERROR_COUNT_CAP, FEC_CORR_BLK_ERROR_COUNT_CAP, FEC_BIT_ERROR_COUNT_CAP

forward error correction.
000a0h DSC_BRANCH_OVERALL_THROUGHPUT_0: 1050 Mp/s Good enough for 5K60Hz (but what's the difference between _0 and _1?
000a1h DSC_BRANCH_OVERALL_THROUGHPUT_1: 2100 Mp/s Good enough for two 5K60Hz displays or one 8K60Hz display (CVT-RB, not HDMI)
000a2h DSC_BRANCH_MAX_LINE_WIDTH: 5120 pixels I guess this is good enough for 5K as long as it's not counting horizontal blanking pixels.

adogwithacat · Mar 23, 2022

joevt said:

I don't know if an MST hub can do two 5K displays.

I have successfully done one 5K display (it's actually dual tile: 483.25MHz per tile = 23 Gbps at 8bpc)
I have successfully done three 4K 533MHz 8bpc displays. That's 38.3 Gbps.

Two 5K 936 MHz 8bpc displays is 44.9 Gbps. Maybe that's not too much. Or maybe it helps that one uses DSC pass thru.

DSC@12bpp can do up to 2160 MHz (HBR3 x4) but there's some overhead unaccounted for in that (3% for FEC. More for MST).
DSC@8bpp can do up to 3240 MHz but you don't get to choose the bpp (except macOS has a preference for changing that which I haven't seen anyone try yet).
https://forums.macrumors.com/thread...-on-mac-pro-yes-you-can.2309750/post-30748427

You have to look at the DPCD registers of the MST hub to see the exact DSC capabilities. AGDCDiagnose in macOS can do that. I added a similar capability in my macOS AllRez utility (I think mine might be easier to read?). I want to find a method to read the DPCD registers of all DisplayPort devices in a DisplayPort tree (you can connect multiple MST hubs together, for example, and some HDMI adapters are actually MST hubs).
https://forums.macrumors.com/thread...-on-mac-pro-yes-you-can.2309750/post-30760662

The DisplayPort 1.4 spec is not available for download so I don't know what all the DPCD registers mean regarding DSC.

Below is sample output from my AllRez command for the MST hub in my HP Thunderbolt Dock G2 connected to an unflashed GC-ALPINE RIDGE in my MacPro3,1 using DisplayPort 1.2 from a EVGA Nvidia GeForce GTX 680.

The BRANCH_OUI and BRANCH_ID show that this is a Synaptics VMM-5333 MST hub.
https://www.synaptics.com/products/video-interface-ics
https://uploadcdn.oneyac.com/attachments/userfile/b4/13/1593672494627_4765.pdf

Actually, I have 3 other MST hubs connected to that MST hub before the display connection but I haven't found a method to read the DPCD from the other devices in the chain yet.

Code:

                DisplayPort = {
                    00000h: 12 14 c4 81 01 11 01 83 2a 3f 04 00 00 00 02 00  ........*?......
                    00020h: 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00060h: 01 21 00 14 0b 00 00 00 01 03 02 11 08 00 00 04  .!..............
                    00080h: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00090h: 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    000a0h: 09 1e 10 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00100h: 14 84 00 00 00 00 00 10 7b 00 00 00 00 00 00 00  ........{.......
                    001c0h: 00 00 3f 00 00 00 00 00 00 00 00 00 00 00 00 00  ..?.............
                    00200h: 01 00 77 77 01 03 22 22 00 00 00 00 00 00 00 00  ..ww..""........
                    00210h: 00 80 00 80 00 80 00 80 00 00 00 00 00 00 00 00  ................
                    00240h: ec fc bc 51 9d 3d 00 00 00 00 00 00 00 00 00 00  ...Q.=..........
                    00280h: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    002c0h: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    004a0h: 54 45 53 4c 41 03 01 10 00 00 00 00 00 00 00 00  TESLA...........
                    004b0h: 94 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00500h: 90 cc 24 53 59 4e 41 53 33 10 05 04 05 00 00 00  ..$SYNAS3.......
                    00560h: 00 01 01 02 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    01400h: 10 14 c9 a0 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    01410h: 00 00 00 00 03 00 87 00 00 00 00 00 00 00 00 00  ................
                    02000h: 00 00 01 00 00 00 00 00 00 00 00 00 77 77 01 03  ............ww..
                    02200h: 14 14 c4 81 01 11 01 83 2a 3f 04 00 00 00 84 00  ........*?......
                    02210h: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    68000h: d9 c8 cd 9c 4a b4 6d 00 00 00 00 00 00 00 00 00  ....J.m.........
                    68020h: 00 00 00 00 00 00 00 00 03 00 01 01 00 00 00 00  ................

                    Receiver Capability
                        00000h DPCD_REV: 1.2
                        00001h MAX_LINK_RATE: HBR2
                        00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                        00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                        00004h NORP: 2
                        00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                        00007h DOWN_STREAM_PORT_COUNT: 3, OUI_SUPPORT
                        00008h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT, ?0x28
                        00009h RECEIVE_PORT_0_BUFFER_SIZE: 2048 bytes per lane
                        0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                        0000eh TRAINING_AUX_RD_INTERVAL: 8ms all
                        00021h MSTM_CAP: MST_CAP
                        00022h NUMBER_OF_AUDIO_ENDPOINTS: 1
                        00060h DSC_SUPPORT: DSC_DECOMPRESSION_IS_SUPPORTED
                        00061h DSC_REV: 1.2
                        00062h DSC_RC_BUF_BLK_SIZE: 1kB
                        00063h DSC_RC_BUF_SIZE: 20 * DSC_RC_BUF_BLK_SIZE
                        00064h DSC_SLICE_CAP_1 & 2: 1, 2, 4 max slices per DisplayPort DSC sink
                        00067h DSC_MAX_BITS_PER_PIXEL: 16 bpp
                        00069h DSC_DEC_COLOR_FORMAT_CAP: RGB, YCbCr 4:4:4
                        0006ah DSC_DEC_COLOR_DEPTH_CAP: 8 bpc
                        0006bh DSC_PEAK_THROUGHPUT: MODE_0 = 340 Mp/s, MODE_1 = 340 Mp/s
                        0006ch DSC_MAX_SLICE_WIDTH: 2560 pixels
                        0006fh DSC_BITS_PER_PIXEL_INC: 1 bpp
                        00080h DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort, HPD aware
                        00090h FEC_CAPABILITY: FEC_CAPABLE, FEC_UNCORR_BLK_ERROR_COUNT_CAP, FEC_CORR_BLK_ERROR_COUNT_CAP, FEC_BIT_ERROR_COUNT_CAP
                        000a0h DSC_BRANCH_OVERALL_THROUGHPUT_0: 1050 Mp/s
                        000a1h DSC_BRANCH_OVERALL_THROUGHPUT_1: 2100 Mp/s
                        000a2h DSC_BRANCH_MAX_LINE_WIDTH: 5120 pixels
                    Link Configuration
                        00100h LINK_BW_SET: HBR2
                        00101h LANE_COUNT_SET: 4, ENHANCED_FRAME_EN
                        00107h DOWNSPREAD_CTRL: SPREAD_AMP_0_5
                        00108h MAIN_LINK_CHANNEL_CODING_SET: SET_ANSI_8B10B, SET_ANSI_128B132B, ?0x78
                        001c2h PAYLOAD_ALLOCATE_TIME_SLOT_COUNT: Time Slot Count of VC Payload Id in DPCD address 2C0h = 63
                    Link/Sink Device Status
                        00200h SINK_COUNT: 1
                        00202h LANE0_1_STATUS: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00202h LANE0_1_STATUS: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00203h LANE2_3_STATUS: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00203h LANE2_3_STATUS: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        00204h LANE_ALIGN_STATUS_UPDATED: INTERLANE_ALIGN_DONE
                        00205h SINK_STATUS: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                        00206h ADJUST_REQUEST_LANE0_1: LANE0 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00206h ADJUST_REQUEST_LANE0_1: LANE1 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00207h ADJUST_REQUEST_LANE2_3: LANE2 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00207h ADJUST_REQUEST_LANE2_3: LANE3 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                        00210h SYMBOL_ERROR_COUNT_LANE0: 0, valid
                        00212h SYMBOL_ERROR_COUNT_LANE1: 0, valid
                        00214h SYMBOL_ERROR_COUNT_LANE2: 0, valid
                        00216h SYMBOL_ERROR_COUNT_LANE3: 0, valid
                        00240h TEST_CRC_R_CR: 0xfcec
                        00242h TEST_CRC_G_Y: 0x51bc
                        00244h TEST_CRC_B_CB: 0x3d9d
                        00282h FAUX_BACK_CHANNEL_SYMBOL_ERROR_COUNT_CONTROL: COUNT_SYMBOL
                        002c0h PAYLOAD_TABLE_UPDATE_STATUS: PAYLOAD_TABLE_UPDATED, PAYLOAD_ACT_HANDLED
                    Sink Device-Specific
                        004a0h : 54 45 53 4c 41 03 01 10 00 00 00 00 00 00 00 00  TESLA...........
                        004b0h : 94 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    Branch Device-Specific
                        00500h BRANCH_OUI: 90-CC-24 = Synaptics, Inc
                        00503h BRANCH_ID: 53 59 4e 41 53 33  SYNAS3
                        00509h BRANCH_HW_REV: 1.0
                        0050ah BRANCH_SW_REV: 5.4
                        0050ch : 05 00 00 00  ....
                        00560h : 00 01 01 02 00 00 00 00 00 00 00 00 00 00 00 00  ................
                    Sink Control
                        00600h SET_POWER: SET_POWER_D0
                    Sideband MSG Buffers
                        01400h SIDEBAND_MSG_DOWN_REP: 10 14 c9 a0 00 00 00 00 00 00 00 00 00 00 00 00  ................
                        01410h : 00 00 00 00 03 00 87 00 00 00 00 00 00 00 00 00  ................
                    DPRX ESI (Event Status Indicator)
                        02002h SINK_COUNT_ESI: 1
                        0200ch LANE0_1_STATUS_ESI: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200ch LANE0_1_STATUS_ESI: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200dh LANE2_3_STATUS_ESI: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200dh LANE2_3_STATUS_ESI: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                        0200eh LANE_ALIGN_STATUS_UPDATED_ESI: INTERLANE_ALIGN_DONE
                        0200fh SINK_STATUS_ESI: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                    Extended Receiver Capability
                        02200h DP13_DPCD_REV: 1.4
                        02201h MAX_LINK_RATE: HBR2
                        02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                        02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                        02204h NORP: 2
                        02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                        02207h DOWN_STREAM_PORT_COUNT: 3, OUI_SUPPORT
                        02208h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT, ?0x28
                        02209h RECEIVE_PORT_0_BUFFER_SIZE: 2048 bytes per lane
                        0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                        0220eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                        02210h DPRX_FEATURE_ENUMERATION_LIST: VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED, VSC_EXT_VESA_SDP_SUPPORTED, VSC_EXT_VESA_SDP_CHAINING_SUPPORTED, VSC_EXT_CEA_SDP_SUPPORTED, VSC_EXT_CEA_SDP_CHAINING_SUPPORTED
                    HDCP 1.3 and HDCP 2.2
                        68000h AUX_HDCP_BKSV: d9 c8 cd 9c 4a  ....J
                        68005h AUX_HDCP_RI_PRIME: b4 6d  .m
                        68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE, BCAPS_REPEATER_PRESENT
                        6802ah AUX_HDCP_BINFO: DEVICE_COUNT = 1, DEPTH = 1
                }; // DisplayPort

Looking at the DSC related registers, we see the following:

00060h DSC_SUPPORT: DSC_DECOMPRESSION_IS_SUPPORTED decompression from the MST hub is supported
00061h DSC_REV: 1.2 1.2 is the latest (or 1.2a?)
00062h DSC_RC_BUF_BLK_SIZE: 1kB ?
00063h DSC_RC_BUF_SIZE: 20 * DSC_RC_BUF_BLK_SIZE 20 kB
00064h DSC_SLICE_CAP_1 & 2: 1, 2, 4 max slices per DisplayPort DSC sink 4 slices is good, 3 possible DisplayPort sinks, 12 slices total?
00067h DSC_MAX_BITS_PER_PIXEL: 16 bpp macOS only uses 12 bpp for DSC.
00069h DSC_DEC_COLOR_FORMAT_CAP: RGB, YCbCr 4:4:4 RGB or 4:4:4 are best color formats (4:2:0 and 4:2:2 would add additional compression but 8bpp would be preferable).
0006ah DSC_DEC_COLOR_DEPTH_CAP: 8 bpc no 10bpc? that's not good. hope it doesn't matter.
0006bh DSC_PEAK_THROUGHPUT: MODE_0 = 340 Mp/s, MODE_1 = 340 Mp/s 340 MHz * 4 slices = 1360 MHz. I guess that's good enough for 5K.
0006ch DSC_MAX_SLICE_WIDTH: 2560 pixels 2560 * 4 slices = 10K. More than what we need.
0006fh DSC_BITS_PER_PIXEL_INC: 1 bpp This means 8,9,10,11,12,13,14,15,16bpp are supported?
00080h DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort, HPD aware hot plug detect.

00090h FEC_CAPABILITY: FEC_CAPABLE, FEC_UNCORR_BLK_ERROR_COUNT_CAP, FEC_CORR_BLK_ERROR_COUNT_CAP, FEC_BIT_ERROR_COUNT_CAP

forward error correction.
000a0h DSC_BRANCH_OVERALL_THROUGHPUT_0: 1050 Mp/s Good enough for 5K60Hz (but what's the difference between _0 and _1?
000a1h DSC_BRANCH_OVERALL_THROUGHPUT_1: 2100 Mp/s Good enough for two 5K60Hz displays or one 8K60Hz display (CVT-RB, not HDMI)
000a2h DSC_BRANCH_MAX_LINE_WIDTH: 5120 pixels I guess this is good enough for 5K as long as it's not counting horizontal blanking pixels.

Got it. I will try it when I get any device. Thx.

Amethyst1 · Mar 24, 2022

joevt said:
Some 5K displays might use 967MHz.

Just checked their EDIDs: the Iiyama XB2779QQS and Planar IX2790 do.

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Possible solutions for my dual 5k monitors

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