MP 7,1 Question about PCIe lane allocation on Mac Pro (2019)

[repoman27]

I have a pretty good handle on how the PCIe slots are allocated, but I was hoping someone with access to a Mac Pro (2019) could help answer the question: how are the built-in PCIe devices (Ethernet controllers, Wi-Fi module, T2 chip, Thunderbolt controller, etc.) connected to the PCH and PEX 8796 PCIe switch?

This info is available from the Terminal using the following ioreg command:

ioreg -xw80 -k IOPCIExpressLinkStatus | grep -e 'IOPCIDevice' -e 'IOPCIExpressLinkStatus'

This should dump a sort of tree showing how everything is hooked up, and if someone would be so kind as to post the output of the ioreg command here, I'd be much obliged.

And as a bonus question, by my count the design of the Mac Pro (2019) requires at least 15 USB 2.0 ports. However, the Intel C621 PCH only provides 14, so there has to be a USB 2.0 hub or discrete host controller somewhere. Where is it?

The USB Device Tree can be viewed in System Information under Hardware > USB. If there is no hub listed by default, plugging a USB 2.0 device into the various USB and Thunderbolt ports and watching to see where it shows up in the tree should work. My guess is that there are hubs located in MPX modules with four Thunderbolt 3 ports, but who knows.

Edit: tried to clarify what the actual question was.