taken from xlr8yourmac.com
Clarification on new G4s - they do not have a DDR frontside CPU Bus - I'm getting lots of mails on this but as you can clearly see from the Apple PowerMac G4 specs page - they note the system bus bandwidth at 1.3GB/sec - clearly indicating that is *not* a DDR system/CPU (frontside) bus. Just like the Xserve, the new G4s use a single data rate system/cpu bus and a DDR memory bus. If the frontside CPU/system bus was DDR it would have much higher bandwidth specs noted. (There is no shipping PowerPC I know of with a DDR FSB yet.)
(quote from
http://www.apple.com/powermac/specs.html)
"Up to 167MHz system bus supporting over 1.3GBps data throughput
256MB or 512MB of PC2100 or PC2700 DDR SDRAM main memory supporting up to 2.7GBps throughput "
Note the DDR memory bandwidth is 2x the system bus bandwidth - because the latter is SDR vs DDR for the memory bus. (The system/cpu bus is not transferring data on the rising and falling edge of the clock pulse as the DDR memory bus does. The system bus and memory bus are separated by the system controller as shown in Apple's own docs.) I don't know why some people refuse to believe this... Ask Apple if you don't believe me or their own system specs. Do the math - bus width in bytes times clock speed and you'll see it's SDR on the system bus. Hopefully next year there will be DDR frontside bus G4 (or G5) CPUs, but they're not shipping yet. (Apple would have used them I'm sure if they were available.)
Although the CPU is the primary "data pump" for applications, etc., the extra memory bandwidth should benefit other I/O and devices that use DMA. The system improvements are welcome changes and I only wanted to clarify my comments earlier today that noted no DDR frontside/system bus to prevent any more emails from people that were mistaken about the fact there is no DDR frontside (system/cpu) bus in the new G4s.