The PPC chips has failed!

[hvfsl]

With all this talk about the PPC970 coming and the fact that the G4 is not as fast as the fastest P4, I thought I would remind people why Apple switched from Moto CISC chips to the PPC RISC. It was to provide a cheaper processor than the CISC pentiums and the RISC PPC as also meant to run faster. Well the PPC does none of these anymore, it is slower and more expensive than x86 chips. This seems to be a recuring theme with Apple (and inventers in general), they invent something that is really good and then dont develop it enough and allow other companies to make better products.

 

[iGav]

So what do you suggest Apple should do??

 

[crassusad44]

So........

The problem with the PPC has been one company... Moto. Since the G4 came out, Moto was the only one left in the game (they cut out IBM, who also was developing the G3). These past years Moto has cut back development on the G4 (that's why were only on 1,42 GHz now, Steve wanted GHz chips when the dual 800 was first announced).

So, what did Apple do? Steve certainly do not like Moto anymore. So he went to IBM. And the result? The PPC970 and the Sahara and Gobi G3s. RISC is better than CISC. We only need a company capable of producing and developing it. That company is IBM. Expect PowerMacs to surpass Pentiums in performace within a short amount of time...

 

[idkew]

you really have no clue what you are talking about do you?

the ppc is not a failed instruction set, it is a very good one. the reasons you put out have nothing to do with PPC and everything to do with a certain company not doing their job to advance the chip. the power5 variant is one of the most powerful chips out there. remember, apple has very little do do with the development of the PPC processor. moto and ibm both research and develop their own, compatible versions. all apple does is purchase many thousnads of them, solder them to a motherboard (or daughtercard... whatever) and sell the prebuilt computer.

blameing apple for the slow evolution of the PPC chip it like blameing a car because the road is bumpy. ford can´t control the surface fo the road. they only make something that uses it.

the speed... not PPC or RISC´s failt. moto´s fault mostly.

the cost... ever hear of economies of scale? when you are stamiping out millions more chips, you can sell them for less. not to mention when your company is bleeding red in the books for so long, you can´t attempt to join into a price war of attrition.

besides, CISC takes more work to do what a RISC processor does in less cycles. in fact, intel has been making their CISC chips more and more RISC´y lately. a testament to RISC´s advantages.

my .02€ (no cent sign in spain have i found...)

 

[melchior]

the potential is still in PPC. it just needs a lot of R&D. do you think intel and amd get faster processors just by clocking up their processor's when buyers are languishing.(is that a word?) moto gave up on the PPC 2 years ago. they laid-off half of the PPC workforce and apple should have started seriously shopping for another major chip manufacurer.

there is no doubt in any technical persons mind the RISC is a superior architecture to CISC and though development is slow it will continue with more optimal performance into the future. have you seen how much power you need for a P4 or Athlon? i could run my house on what on of those things needs!

 

[mim]

Originally posted by melchior
moto gave up on the PPC 2 years ago. they laid-off half of the PPC workforce and apple should have started seriously shopping for another major chip manufacurer.

I think they probably did, which is why we're hearing about the 970 now. I'd guess that IBM had the option of extending their 750's etc (which it seems they're going to do anyway) or come up with a new design entirely.

So sure the 970 is based of the power4, but it's still a whole new chip that needed research and development. The line does seem to have a lot of potential though.

 

[melchior]

yeah, i agree. potential is the Power4's best attribute right now.

 

[Freg3000]

The best thing with IBM is the future. We can actually see a Power 5 derivative, the 980, and perhaps even a 990, which in a Page 2 Rumor could run up to 6 GHz. That is what I am most excited about-the future.

 

[GeeYouEye]

Just out of curiosity, why is this in Mac Help/Questions and Tips?

 

[tjwett]

seriously, this thread is kind of a jokeypoo. the PPC is wonderful technology, it's Motorola that sucks. what is this dude talking about?

 

[Snowy_River]

Interesting how the original poster has not made any new comments after his first, rather baseless diatribe putting down the PPC architecture.


60...

 

[Wyrm]

CISC assumes memory is expensive, chips aren't pipelined, and programs are hand written in assembler.

RISC assumes memory is cheap, pipelining or super-pipelining is the best way to increase performance, and compilers will be generating code.

(EPIC assumes you have more memory than brains, parallelism rather than MT or MP is the key to performance, and it would be impossible to write code without a compiler)

RISC is not inherently faster or slower at computations than CISC, but the decode stage of the RISC instruction is simplified. That's it! The RISC design freed up the transistor budget for other things, like more registers, pipelining, etc (which are ISA independent).

Since RISC inherently take more instructions that CISC, (think of the CISC decoder as a decompressor), the biggest problem with RISC has been the bandwidth from memory to the cpu. You have to transfer more instruction data than a CISC machine does.

With the new RISCy designs of x86 chips, all these points disappear except for bandwidth - <PPC chips would do well to load compressed programs, because the x86 can do it>.

So the best thing Apple could do is use a processor that increases the bandwidth.

-Wyrm

 

[yzedf]

Originally posted by idkew
the cost... ever hear of economies of scale? when you are stamiping out millions more chips, you can sell them for less. not to mention when your company is bleeding red in the books for so long, you can´t attempt to join into a price war of attrition.

Using your theories a P4 should cost less than a comparable AMD Athlon XP chip...

 

[cb911]

yeah, Apple made a mistake a while back. but at least at WWDC we'll see if Apple will pick up the pace.

and Snowy_River, 60...? are you counting down to something? would all be revealed if i had a look at your profile?

edit>> Snowy_River, i just checked you profile. counting down to the magical 500, eh? got a 'tar all lined up?

 

[5300cs]

Everyone, forgive my ignorance.
Just for the record. ..

G3 = Motorola
G4 = IBM

is this correct, or did they both work on both chips together?

 

[icetraxxg5]

Originally posted by 5300cs
Everyone, forgive my ignorance.
Just for the record. ..

G3 = Motorola
G4 = IBM

is this correct, or did they both work on both chips together?

umm... that would be G3=IBM and G4=Motorola !!!

The slow G4 is the reason why Apple is looking to switch to the IBM PowerPC 970.

 

[physicsnerd]

Umm, I think I'll bite on this one. Okay, if the PPC has failed then why is IBM starting shipments of Power4 systems at 1.3ghz on June 14th,

http://www.serverworldmagazine.com/newsflash2/2002/04/29_ibmi890.shtml

while Intel is shipping Itanium 2 chips at 1ghz?

http://www.intel.com/design/itanium2/prodbref/

In the high end processors the PPC is running at higher clock speeds. So does this make RISC better then EPIC? I don't think so. The G4 isn't as fast as the P4, So? That doesn't make the PPC inferior. I think most everyone wants to see the G4 retired from the top of the line macs. It was a fast chip a few years ago, but its time to move on.

Physicsnerd
-------------------
"Even logic must give way to physics" - Spock

 

[5300cs]

Originally posted by icetraxxg5
umm... that would be G3=IBM and G4=Motorola !!!

The slow G4 is the reason why Apple is looking to switch to the IBM PowerPC 970.

Thanks for clearing that up

 

[MisterMe]

Originally posted by Wyrm
CISC assumes memory is expensive, chips aren't pipelined, and programs are hand written in assembler.

RISC assumes memory is cheap, pipelining or super-pipelining is the best way to increase performance, and compilers will be generating code.

(EPIC assumes you have more memory than brains, parallelism rather than MT or MP is the key to performance, and it would be impossible to write code without a compiler)

RISC is not inherently faster or slower at computations than CISC, but the decode stage of the RISC instruction is simplified. That's it! The RISC design freed up the transistor budget for other things, like more registers, pipelining, etc (which are ISA independent).

Since RISC inherently take more instructions that CISC, (think of the CISC decoder as a decompressor), the biggest problem with RISC has been the bandwidth from memory to the cpu. You have to transfer more instruction data than a CISC machine does.

With the new RISCy designs of x86 chips, all these points disappear except for bandwidth - <PPC chips would do well to load compressed programs, because the x86 can do it>.

So the best thing Apple could do is use a processor that increases the bandwidth.

-Wyrm

But you assume no design consequences for the choice of CISC or RISC. There are and that is why CISC is dying. The dramatic increase in the number of available registers means that values can be stored on chip rather than main memory. RISC mandates that all mathematical operations are performed on values stored in registers rather than main memory. As register math is dramatically faster than memory math, RISC is inherently faster at mathematical operations, clock cycle for clock cycle.

 

[Snowy_River]

Originally posted by cb911
yeah, Apple made a mistake a while back. but at least at WWDC we'll see if Apple will pick up the pace.

and Snowy_River, 60...? are you counting down to something? would all be revealed if i had a look at your profile?

edit>> Snowy_River, i just checked you profile. counting down to the magical 500, eh? got a 'tar all lined up?

I have a couple to choose from. Like many others I'll probably cycle through them...


39...

 

[Wyrm]

Originally posted by MisterMe
But you assume no design consequences for the choice of CISC or RISC. There are and that is why CISC is dying. The dramatic increase in the number of available registers means that values can be stored on chip rather than main memory. RISC mandates that all mathematical operations are performed on values stored in registers rather than main memory. As register math is dramatically faster than memory math, RISC is inherently faster at mathematical operations, clock cycle for clock cycle.

You haven't kept up with modern processor design.

I admit, people in the 90s thought points like yours would be the nail in the CISC coffin, but they've been left scratching their heads wondering why the x86 is still around. The truth is, the ISA is fairly irrelevant (as long as it Turing complete) - so the thread subject is really quite incorrect. Sure it makes some things easier, or some things harder, but that's where designers can go to work. Take a look at any modern chip and you'll see they pretty much employ similar techniques for getting the job done, or employ tricks for minimizing or eliminating a disadvantage; renaming registers, out-of-order scheduling, micro ops, multi-threading, low latency cache, trace cache, just to name a few. It really comes down to how many engineers you are willing to throw at a problem. Intel plainly has more, but IBM has enough to make things interesting.

It is ironic that Intel taught the world that an old design could be extended literally forever, when they are trying to push the new EPIC IA64 as key to performance. It will be interesting to see what a fight the POWER series puts up against the Itanic, or even its own x86 line. I would have liked to see Intel push a nice RISC design beyond the i860 - but I guess they thought they were stepping on their own toes.

RISC does have one serious disadvantage that I can think of and that is code size. RISC code tends to bloat faster than CISC code does, and unless you have the means to shovel the data between the CPU and memory faster than a CISC chip, then you have a problem. Last I looked, x86 has reached QDR 200Mhz, while the G4 PPC is SDR 167Mhz (and that is beyond spec) - oops.

But again - bus speeds are ISA independent, and have nothing to do with RISC or CISC. Just better technology and engineering.

I always thought a great PPC extension would be to load compressed code and have it decompress onchip - that might go to help with the bandwidth problem - but then might as well implement instruction macros or something and make the PPC decode stage just as complicated as the x86.

-Wyrm

 

[MisterMe]

Originally posted by Wyrm
You haven't kept up with modern processor design.

....

-Wyrm

More like modern marketing hype. The truth is that which works. When you want a no compromises computer, you don't go with the eMachines from Office Depot or even the AlienWare from Best Buy. You go with Sun, IBM, or even SGI. In the case all of these, their topline comptuters are based on RISC processors. Can you sit there and somehow claim that anything out of Intel is more modern than the Power III, the Power4, the PowerPC 970, the upcoming Power 5, or the latest version of UltraSPARC, or MIPS? Get real.

 

[Wyrm]

Originally posted by MisterMe
More like modern marketing hype. The truth is that which works. When you want a no compromises computer, you don't go with the eMachines from Office Depot or even the AlienWare from Best Buy. You go with Sun, IBM, or even SGI. In the case all of these, their topline comptuters are based on RISC processors. Can you sit there and somehow claim that anything out of Intel is more modern than the Power III, the Power4, the PowerPC 970, the upcoming Power 5, or the latest version of UltraSPARC, or MIPS? Get real.

You should get real.

Comparing a desktop PC to a server?

Why are you limiting your "no compromise machine" to the middle range RISC boxes? Expand your mind: You could also go with a Dell x86 server, or an HPAQ x86 server, or an IBM x86 server or one of many others out there. Opteron servers hello? Or you could go the opposite side of the spectrum and get a IBM S/390, an NEC SX. Expensive as snot, but blow anything Sun, or SGI have out of the water right now... Sunfire?.. please!

RISC doesn't mean high end either - look at ARM.

My point is that RISC/CISC doesn't matter (RISC/CISC IS marketing hype). It might have when the decoder was a large chunk of silicon (% wise), but now it isn't. Now it is just going to be a game of tricks and good design in other places in the processer. The decoder just provides an "emulation layer" in front of the real processor. Intel has been using microcode for quite a while, and even the blessed POWER4 and PPC970 use this trick. You can make a new ISA, maybe to make things easier, but you are not going to achieve magnitudes greater performance because of the ISA.

RE: more modern than a xxx?
When Intel can make the x86 faster than the RISC designs at a cheaper cost, my hats off to them. It is a harder problem, so I'd have to say they have some really good engineers, and lots of them. I don't think anything can touch the P4 for integer math, and no RISC chip can touch the price (hey wasn't RISC supposed to be cheaper?).

-Wyrm