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Thunderbolt 4 ports on the M2 Mini
- Thread starter hajime
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Using a hub/dock might slow the speeds of external drives, etc. I've experienced this first-hand with my SanDisk 1 TB SSD, where if I have it plugged in directly to a USB-C port (the SSD isn't Thunderbolt), it gets the near-native speeds. However, when I plug it into a hub, it gets 50% of the native speed, so I'm losing quite a bit of performance when plugged into a hub. It could be a bottleneck with the hub though because it's a cheap piece of s**t. That's the difference I see every day, but there are probably many other differences I'm unaware of.
The devices connected to the Thunderbolt dock would be sharing the bandwidth from one of the Thunderbolt ports on the Mac mini.
Each Thunderbolt port on Apple Silicon Macs have dedicated bandwidth that’s not shared with the other ports.
Total bandwidth of M2 Mac mini with two Thunderbolt 4 ports: 80Gbps
Total bandwidth of M2 Pro Mac mini with four Thunderbolt 4 ports: 160Gbps
True that! Say for example I have three SSDs. Here's the difference:
- All 3 plugged directly into TB4 ports on Mac mini = if I copy some files over to all three, it theoretically would copy at native speeds to all three (I don't know for sure)
- All 3 plugged into hub = if I copy files to all three, it's going to split bandwidth between the SSDs.
More like 44 Gbps for M2 and 88 Gbps for M2 Pro since data is limited to ≈22 Gbps per port (or maybe 24 or 25 Gbps in some cases).
The rest of the bandwidth of a Thunderbolt port can only be used for displays. The M2 and M2 Pro can only connect two displays to Thunderbolt. Display bandwidth is pixel clock x bits per pixel. bits per pixel is usually 30 but can be reduced to 12 for displays that support DSC.
4K60 = 16 Gbps
5K60 = 29 Gbps (LG UltraFine 5K - no other display can be connected to the same Thunderbolt port)
5K60 = 11 Gbps (Apple Studio Display)
6K60 = 15.4 Gbps (Apple Pro Display XDR)
Display bandwidth is mostly one way so it might reduce write performance if it exceeds 18 Gbps but have little effect on read performance.
To pass Thunderbolt 4 certification each TBv4 must be able to provide DisplayPort output. Either Apple is not passing TBv4 certification (and blowing smoke on specs page) or you can get as many displays as there are TB ports. Which means M2 Pro can do 4 display.
I think Apple's Tech specs page is more of a marketing specs page. They are trying to sell stuff more than trying to outline the strictly technical specifications. The max number of 6K ( 'buy me I'm super expensive') displays. shouldn't be the baseline counting metric on the Mini's tech spec page.
"
... [ column M2 ]
Display Support
Simultaneously supports up to two displays:
- One display with up to 6K resolution at 60Hz over Thunderbolt and one display with up to 5K resolution at 60Hz over Thunderbolt or 4K resolution at 60Hz over HDMI
- Support for native DisplayPort output over USB‑C
- Support for one display with up to 4K resolution at 60Hz
[ column M2 Pro ]
Simultaneously supports up to three displays:
- Up to three displays: Two displays with up to 6K resolution at 60Hz over Thunderbolt and one display with up to 4K resolution at 60Hz over HDMI
- Up to two displays: One display with up to 6K resolution at 60Hz over Thunderbolt and one display with up to 4K resolution at 144Hz over HDMI
- One display with up to 8K resolution at 60Hz or 4K resolution at 240Hz over HDMI
- Support for native DisplayPort output over USB‑C
Mac mini - Technical Specifications
See all the technical specifications for Mac mini with the M4 or M4 Pro chip.
www.apple.com
What is buried here is the "Thunderbolt 4 digital video output... native DisplayPort.. ". Each USB-C socket should do Display at some minimal bandwidth level.
What might happen though is that to light up the 2nd or 4th TB socket is that the HDMI socket goes "dead". One of those DisplayPort feeds is going to have to get shared. If Apple is sharing one DP feed for every dual USB-C socket what they have is USB4 not TBv4.
However, one of the differences between USB4 sockets and Thunderbolt 4 socket is the latter is not suppose to under provision video out. That's way the previous M1 systems were "USB4 with Thunderbolt (3) ". They didn't meet TBv4 standards.
P.S. The differences between TBv4 and TBv3
Frequently Asked Questions (FAQs) | Thunderbolt Technology Community
Can get away with starving off a port from video is a USB4 thing, not a TBv4 compliance.
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That table very specifically says "Minimum PC video requirements". That implies for the whole PC and not for individual ports. Apple doesn't call the M2 MacBook Air Thunderbolt 4 because they only support one external display. But for the M2 Pro and Max they seem to be covered.To pass Thunderbolt 4 certification each TBv4 must be able to provide DisplayPort output. Either Apple is not passing TBv4 certification (and blowing smoke on specs page) or you can get as many displays as there are TB ports. Which means M2 Pro can do 4 display.
Frequently Asked Questions (FAQs) | Thunderbolt Technology Community
www.thunderbolttechnology.net
Can get away with starving off a port from video is a USB4 thing, not a TBv4 compliance.
Edit: To clarify that I meant the M2 MacBook Air and not the new M2 Mac mini.
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That is nonsense. It can't be the whole PC including other ports not in the standard. The TB standard is for the TB infrastructure. That' it. TB can't specify 'oh you gotta put another HDMI port" on the box (something not directly coupled to Thunderbolt).
You can spin this as the "whole TB port provisioning infrastructure" . So across all the Thunderbolt ports it would be a minimum of 2. So if a PC as 4 ports provisioned out of a SoC you can expect a minimum of 2. Kind of maps cleanly to a hub having four ports then maybe can get 2 ports out of that if the host is fully TBv4 complaint no other consumers on another daisy chain.
Go take a look at the Specs page. Apple does call the ports on the M2 Mini Thunderbolt 4 ports. That is a change from the M1 Mini. Either the M2 video out subsystem has been upgraded or Apple is duplicitously misusing the label.
if upgraded for two , then pretty likely upgraded for 4 also.
[ The M2 MBA and MBP 13" still 'fail" at TBv4 certification because the internal screen draws off enough DP output resources. The Mini has no screen. There is little good design reason why it needs to be similarly hobbled. Apple had to get the M1 'out the door' so could skip some limited dP output redirect.... but by second generation and bigger transistor budget that is just lame. ]
four 2K or 1080p display being driven really shouldn't be that hard of a load. Apple doesn't sell those, so they don't want to talk about them on the Specs page. But a reasonable implementation should be able to muster that configuration. Intel does it. AMD does it.
P.S. That table is somewhat implictly about per Thunderbolt controller. If look at the PCI-e backhaul requirements. That isn't a per PC or per entire aggregation of ports constraint. It is a per controller constraint.
historically controllers covered a pair of ports. The integrated into the SoC ones are controller / port.
[ Not that Apple provides the entire DisplayPort multiple screen per stream standards support. ]
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Pretty sure they do certify the whole PC solution. For instance, they make it a requirement to have Intel VT-d DMA protection, that has nothing to do with the port but it is in the controller and the operating system.
They also make systems have at least one charging (Thunderbolt) port, they don't make it required to have every port have charging, for computers that use less than 100 watts.
- PC charging on at least one computer port. (For thin-and-light laptops that require less than 100 watts to charge.)
Certification | Thunderbolt Technology Community
I don't have the spec, but it certainly has to be more nuanced than that.
Otherwise, Thunderbolt hubs wouldn't be permissible. How could a 3-port Thunderbolt 4 hub ever be certified, with no knowledge of the display support of the host it is connected to? Or what if three hubs were daisy-chained, do we require the host to support 7x displays from one port?
Specifying that every port can support video, but not requiring every port to support video simultaneously, is the only thing that makes sense from a sane graphics resources perspective.
It's quite clear that the PC only needs to be able to output two 4K displays in total to be certified TB4.
The base M2 Mac mini does that. Apple far exceed that with support for one 6K and one 5K simultaneously over the two TB ports.
The base M2 Mac mini does that. Apple far exceed that with support for one 6K and one 5K simultaneously over the two TB ports.
The change is that on the M2 Mac mini you can use both Thunderbolt 4 ports to drive two displays where previously it was one display on TB3 and one on HDMI. Now if you use both TB4 ports to drive displays, the HDMI port is unused.
More precisely, two 4K60 10bpc RGB displays from a single Thunderbolt port. This requirement means the Thunderbolt controller has two DisplayPort inputs and supports 40 Gbps. I suppose there's a seperate requirement that it can support HBR3 DisplayPort input (8K30 or 4K120).
It doesn't need to be able to do two 4K60 displays from all Thunderbolt ports. For example, Intel Maple Ridge Thunderbolt 4 controller can do two 4K60 displays from a single Thunderbolt port or one from each Thunderbolt port but it can't do 4 total displays (two displays per Thunderbolt port).
Using your formula and value (pixel clock x 12 bits per pixel for DSC), I get the same result as you for the ASD, but not for the XDR:
ASD: 5120 x 2880 x 60 x 12/10^9 = 10.6 Gbps
XDR: 6016 x 3384 x 60 x 12/10^9 = 14.7 Gbps
Also, does the fact that the XDR has a true 10-bit panel (as compared with the 8 bits +FRC used by the ASD) have any effect on bandwidth?
Elsewhere, you wrote that DP 1.4 allows "25.92 Gbps of video data before 8b/10b encoding". Does that mean we need to adjust that 25.92 Gbps figure and, if so, what is the bottom-line max video bandwidth of DP 1.4 and DP 2.0? I'm curious because I'm wondering what's the most each can drive without DSC.
You're only including active pixels. Some time is reserved for horizontal and vertical front porch, sync width, and back porch.
For 6K60:
6016x3384@60.000Hz 210.960kHz 1286.01MHz h(8 32 40 +) v(118 8 6 -)horizontal front porch is 8, horizontal sync width is 32, horizontal back porch is 40. Total = 6096.
vertical front porch is 118, vertical sync width is 8, vertical back porch is 6. Total = 3516.
XDR: 6096 x 3516 x 60 x 12/10^9 = 1286.012160MHz x 12bpp = 15.4 Gbps.
8 bits + FRC or true 10bit use the same bandwidth. All 10bpc are transmitted and the display decides what to do with the bits.
25.92 Gbps is the amount of data that can be sent for HBR3. Pixels are data. No adjustment is required, unless the data requires extra processing (if FEC is added).
The 25.92 Gbps of data is turned into 32.4 Gbps on the wire because it takes 10b on the wire to encode 8b of data. This 8b/10b encoding doesn't exist while DisplayPort is tunnelled over Thunderbolt since Thunderbolt has its own method (64b/66b) of encoding bits on the wire.
DSC is usually combined with FEC (Forward Error Correction) which requires a small amount of overhead.
DisplayPort 2.0 uses 128b/132b encoding = 0.9696969696%. But there's some additional overhead (FEC is always enabled) that makes this more like 96.7%. So UHBR20 which is 80 Gbps on the wire is ≈77.37 Gbps of data.
https://en.wikipedia.org/wiki/DisplayPort
I'm curious why a TB3/4 controller's 40 Gbps on the wire doesn't enable ≈77.37/2 = 38.69 Gbps of video data. Is it because TB3/4 doesn't have its own video protocol, and is thus limited to VESA's HBR3?
Given what you said about TB tunneling, if you are driving a montitor using a TB port, even with HBR3's 32.4 Gbps cap, why isn't the data transmission limit 32.4*64/66 ≈ 31.4 Gbps (less overhead) rather than 25.92 Gbps?
And what's your basis for assuming a 30/12 = 2.5:1 compression ratio for Apple's DSC implementation? Has Apple said this is what they use?
I've seen 3:1 quoted as the maximum compression ratio for DSC, but if you're starting with 30 bits per pixel, the following table suggests 3.75:1 is the maximum. [VESA claims these are all visually lossless, but I would want to see multiple reliable independent studies before accepting this, particularly at the highest compression ratios.]
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Right. Thunderbolt uses DisplayPort for video. Thunderbolt controllers currently handle two HBR3 x4 DisplayPort inputs. A GPU can send 25.92 Gbps of data to each input of the Thunderbolt controller as 32.4 Gbps HBR3. The Thunderbolt controller takes the 32.4 Gbps input and tunnels the 25.92 Gbps result. A Thunderbolt controller at the other end of the tunnel restores the 8b/10b encoding used by the display.
The 64b/66b encoding is for Thunderbolt data only. The GPU connected to the host Thunderbolt controller and the display connected to the peripheral Thunderbolt controller rely on DisplayPort 8b/10b encoding. Also note that Thunderbolt is actually 41.25 Gbps on the wire. The 40Gbps number is before the 64b/66b encoding is applied. Thunderbolt is maybe the only protocol that uses the pre-encoding bandwidth number when discussing it's link rate. USB 5 Gbps is actually 4 Gbps. USB 10 Gbps is actually 9.7 Gbps (actually more than twice is fast a USB 5 Gbps), SATA 6G is actually 4.8 Gbps, etc.
A Thunderbolt controller can have multiple Thunderbolt ports (usually no more than two) so that it could send 25.92 Gbps to one port and 25.92 Gbps to the other port. For a single port, Thunderbolt can send two HBR2 x4 connections of 17.28 Gbps each, or it can send one HBR3 and one HBR connection - whatever will fit in the 40 Gbps limit. Usually the limit is 34.56 Gbps for two DisplayPort connections over Thunderbolt.
However, Apple can force two HBR3 connections over Thunderbolt for the Apple Pro Display XDR to support dual tile mode. One would think that two HBR3 connections would require 51.84 Gbps, but each tile of the XDR is only 648.91MHz (19.4673 Gbps) and Thunderbolt does not transmit the DisplayPort stuffing symbols that are used to fill the DisplayPort link rate. The stuffing symbols are recreated at the end of the tunnel. So the XDR can use 38.9346 Gbps of Thunderbolt in this mode.
If you use an app like AllRez to look at the info provided by macOS on an Intel Mac about a display that is using DSC, you can see that the framebuffer is using 12bpc (36 bpp) and that DSC is using a target bpp of 12 which means the compression ratio is 3:1.
There may be a preference in
com.apple.CoreDisplay called dscTargetBPP that may allow changing the default from 12 to something else. Maybe 8 can work? I haven't checked when this preference actually gets used. I think CoreDisplay is for Intel Macs only?VESA does have samples and source code on its website (free downloads section) so you can create and compare images using different target bpp.
EDIT (Oct 3, 2024):
Turns out that the dscTargetBPP preference can only be changed if the Apple Internal SIP bit is set, and that bit cannot be set by csrutil. I don't know how to change that bit.
My WhateverGreen fork (Intel Macs only) has a new patch to change dscTargetBPP (add a boot-arg
dscbpp=8 - for Catalina and later). If you're using Open Core or OCLP, then you can replace Lilu and WhateverGreen with my versions. If you use any other Lilu based kexts then they need to be recompiled using the headers from my Lilu.kext. That patch, in conjunction with the CheckTimingWithRange patch (add a boot-arg -cdfon - For Tiger and later), can enable 4K240 and beyond on Intel Macs with a GPU that supports DSC (tested with 6800XT and Sequoia). DP to HDMI adapters are not tested.I think Apple Silicon Macs automatically support DSC with values ≤ 12 (4K240 tested on M3 with Sequoia).
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I did a bit more reading and came up with this summary of encoding:
Unacceptable DC bias can occur when transmitting digital data, if the numbers of 0's and 1's get too far out of balance. To avoid this, transmision schemes typically add dummy bits that can be set to offset the bias (e.g., 8b/10b encoding provides two dummy bits for every 8b word). But this requires more bandwidth. When TB gives their 40 Gbps bandwidth, that's for the data only. But the other major standards (including USB, SATA, DP, and HDMI*) fudge this by quoting the pre-encoding bandwidth, i.e., by including the dummy bits.
*HDMI 2.1's "48 Gbps" is actually 42.0 Gbps of usable data ( https://en.wikipedia.org/wiki/HDMI )
Ah, cool. So if you had two different displays that each needed, say, 19 Gbps, you couldn't drive both using two HBR3 connections on a single TB controller, because the DP protocols would require each HBR3 connection to be assigned 25.92 Gbps, i.e., you can't defeat the DP stuffing symbols with two different connections. But you can with a single connection, for displays that allow dual tiling.
This also means that Macs always drive the XDR without DSC (unless, as was discussed above, your Mac supports DSC, and you're using a TB dock to drive two XDR's on a single port, like with the CalDigit TS4: https://www.caldigit.com/thunderbolt-station-4/). That's how Apple is able to support the XDR on all these Macs, most of of which don't have DSC. And it also explains why Apple chose the XDR's unique 6k resolution—it was the highest res they could achieve with 60Hz/10bpp without needing DSC.
[NB: Apple also officially supports the XDR on the following Macs, but only with resolutions <6k: iMac Pro (2017); Mac Mini (2018); 13" MBP (2016–2019); 13" MBP with two TB3 ports (2020). I believe all of them have 40 Gbps TB3, but apparently the implementation you described to enable a 38.9346 Gbps data rate can't be done with them.]
Here I'm confused. The actual uncompressed data volume is 30 bpp (thats how you got 38.9346 Gbps for the uncompressed XDR). So if, with DSC, you're instead transmitting 12 bpp, the true compression ratio (original data volume/transmitted data volume) is 2.5:1, no?
Or is this a case analogous to the way DP, etc. fudge the bandwidth? I.e., just as they are including extraneous dummy bits to inflate the link rates, is VESA including extraneous bits (in this case, the added 4 bpp needed for the frame buffer) to inflate the compression ratio?
*******
I wonder how Apple will handle the expected 120 Hz 5k monitor, which requires ~55 Gbps uncompressed. Will they introduce it alongside a DP 2.0-capable Mac Pro? And for backwards compatability, will they use standard DSC compression (~22 Gbps), which would enable them to transmit it with a single HBR3 link? Or will they make use of a scheme like what they do with the XDR, which would enable a lower compression ratio to reduce the potential for artifacts? Does DSC offer lower compression ratios?
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The new XDR is rumored to be 7k, and also possibly 120 Hz. If they do use that res, I wonder if that's because it's also about the highest that can be run uncompressed at 120 Hz under TB5 (max data rate 120 Gbps, https://arstechnica.com/gadgets/202...ec-triples-bandwidth-to-120gbps-with-a-catch/ ). Extrapolating from the 6k data rate:
7k uncompressed @ 120 Hz: 39 Gbps x (7/6)^2 x 2 ~ 106 Gbps
7.4k uncompressed @ 120 Hz: 39 Gbps x (7.4/6)^2 x 2 ~ 119 Gbps
8k uncompressed @ 120 Hz: 39 Gbps x (8/6)^2 x 2 ~ 139 Gbps
But how would that work if TB5 is limited to using DP 2.0's UHBR20 (77 Gbps)? Are they going to tile the display like they do now with the XDR under TB4 & HBR3? Or will TB5 have its own video protocol so tiling is not needed?
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Right. HDMI 2.1 uses 16b/18b encoding so it would be 42.6666667 Gbps but it may use FEC which reduces that to ≈42 Gbps.
I suppose if Apple can force dual HBR3 for a single display, they could do it for two displays. But they only choose to do it for the two tiles of a single Apple Pro Display XDR.
DP stuffing symbols are never transmitted over Thunderbolt. This means two HBR2 displays can use different amounts of bandwidth over Thunderbolt depending on pixel clock and bits per pixel.
Not sure why you included the "and you're using a TB dock to drive two XDR's on a single port" part. Since the XDR uses DSC, you can connect two to a single Thunderbolt port. Or, if you have two XDRs running at 6K60 connected to the same Thunderbolt port, then it means they must be using DSC.
Mac mini 2018 and 13 inch Mac Book Pro has Intel Graphics which is limited to HBR2.
iMac Pro 2017 has Alpine Ridge Thunderbolt controller which is limited to HBR2. I'm not sure if there's an HBR3 capability for directly connected displays?
No extraneous bits. The framebuffers are different.
Dual HBR3 outputs 30bpp from a 30bpp framebuffer.
HBR2 with DSC outputs DSC@12bpp from a 36bpp framebuffer.
On intel Macs, the default for DSC is always 12bpp. I suppose Apple could add special cases for specific displays when they are created. DSC@16bpp should be possible. I think the max is 63.9375 bpp (includes 4 fractional bits).
5K120 using DSC@12bpp only requires 22.83 Gbps so it won't require DP2.0.
You should use a CVT-RB2 timing calculator. You can download and install edid-decode.
Code:
width=$((7 * 1024))
height=$((width * 9 / 16))
refresh=120
edid-decode --cvt w=$width,h=$height,fps=$refresh,rb=2
CVT: 7168x4032 119.999978 Hz 16:9 512.160 kHz 3712.135000 MHz (RBv2)
Hfront 8 Hsync 32 Hback 40 Hpol P
Vfront 222 Vsync 8 Vback 6 Vpol N
pixelclock=3712.135000 # MHz
bc <<< "scale=3; $pixelclock * 12 / 1000"
44.545 # Gbps
bc <<< "scale=3; $pixelclock * 30 / 1000"
111.364 # GbpsTwo choices, just like for 6K: tile or DSC.
TB5 will not have a new video protocol.
Sorry for the delayed response. I corrected a typo (see strikeout) in case that was causing the confusion.
Anyways, what I meant was that, based on what you showed, DSC is not necessary when driving a single XDR. Hence I assumed that, even if a Mac is DSC-capable, it's only going to be using DSC with the XDR when you are driving more than one XDR on a single port (or, more generally, if you are driving an XDR plus any other monitor on that port).
Or is that not correct? Do DSC-capable Macs use DSC when driving only a single XDR on a TB port, even if that's not necessary? And if so, why?
OTOH, if a single XDR doesn't use DSC even on DSC-capable Macs, what about the 6k Dell?
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