Thunderbolt Retimer?

[Pro7913]

Intel® JHL8040R Thunderbolt™ 4 Retimer - Product Specifications | Intel

Intel® JHL8040R Thunderbolt™ 4 Retimer quick reference with specifications, features, and technologies.

ark.intel.com

Does anyone know what this is?

 

[Quu]

This chip is a Retimer which is a generalised name for a device in this case a microchip which repeats a signal.

Its job is to allow for more flexible board designs by effectively increasing the maximum trace distance allowed between the Thunderbolt controller and the Thunderbolt port on the physical device.

This specific chip has been developed to help Intel integrate the Thunderbolt controller into their CPU's which they have done with the upcoming Icelake chips. Normally if you look at a motherboard which has Thunderbolt 3 they put the Thunderbolt controller as physically close to the port on the device as possible to reduce signal degradation caused by long traces (the metal lines inside the PCB that carry the signals).

Since the CPU's will now have the Thunderbolt controller embedded into them the distance will be much greater in most designs if they keep to the same layouts we've come to expect in desktop and laptop computers. Thus the need for a retimer chip which the JHL8040R is.

 

[Pro7913]

This chip is a Retimer which is a generalised name for a device in this case a microchip which repeats a signal.

Its job is to allow for more flexible board designs by effectively increasing the maximum trace distance allowed between the Thunderbolt controller and the Thunderbolt port on the physical device.

This specific chip has been developed to help Intel integrate the Thunderbolt controller into their CPU's which they have done with the upcoming Icelake chips. Normally if you look at a motherboard which has Thunderbolt 3 they put the Thunderbolt controller as physically close to the port on the device as possible to reduce signal degradation caused by long traces (the metal lines inside the PCB that carry the signals).

Since the CPU's will now have the Thunderbolt controller embedded into them the distance will be much greater in most designs if they keep to the same layouts we've come to expect in desktop and laptop computers. Thus the need for a retimer chip which the JHL8040R is.

They named it as Thunderbolt 4 retimer. Any idea why?

 

[Quu]

They named it as Thunderbolt 4 retimer. Any idea why?

It's likely due to the way Icelake sends 4 lanes to the retimer. These retimers are basically required for Icelake Thunderbolt 3 usage.

Intel won't be supporting PCIe 4.0 on any of their chips for a while, even Icelake is still PCIe 3.0 and Thunderbolt 4 (when released) will require PCIe 4.0 for operation as they won't widen the bus, it will stay at 4 lanes so the only increase in speed will come from doubling of the available bandwidth over the same four lanes.

Here is some more info about the retimer and its place in the Icelake product stack: https://fuse.wikichip.org/news/2628/a-look-at-the-ice-lake-thunderbolt-3-integration/

 

[Pro7913]

It's likely due to the way Icelake sends 4 lanes to the retimer. These retimers are basically required for Icelake Thunderbolt 3 usage.

Intel won't be supporting PCIe 4.0 on any of their chips for a while, even Icelake is still PCIe 3.0 and Thunderbolt 4 (when released) will require PCIe 4.0 for operation as they won't widen the bus, it will stay at 4 lanes so the only increase in speed will come from doubling of the available bandwidth over the same four lanes.

Here is some more info about the retimer and its place in the Icelake product stack: https://fuse.wikichip.org/news/2628/a-look-at-the-ice-lake-thunderbolt-3-integration/

How come TB4 requires PCIe 4.0? Bandwidth issue?

 

[Quu]

How come TB4 requires PCIe 4.0? Bandwidth issue?

Well with each version of Thunderbolt they have increased its speed. And those speed increases have traditionally been tied to the PCIe specification available at the time except with the move from Thunderbolt 1 to 2 where they merged upstream and downstream channels so that the bandwidth can be dynamically assigned.

So it went like this:
Thunderbolt 1: 10Gb/s up, 10Gb/s down. PCIe 2.0 x4
Thunderbolt 2: 20Gb/s up or down but not at the same time. PCIe 2.0 x4
Thunderbolt 3: 40Gb/s up or down but not at the same time. PCIe 3.0 x4

So the next Thunderbolt specification will most likely be:

Thunderbolt 4: 80Gb/s up or down but not at the same time. PCIe 4.0 x4

There's not really much they can do with the standard beyond increasing its speed at this point. It can already deliver 100 Watts of power, it's already hot-pluggable, it has a very robust and interchangeable connector, it's extremely low latency.

AMD already is shipping PCIe 4.0 equipped processors today (Ryzen 3000, Threadripper 3 and EPYC all support this) but the Thunderbolt standard was only opened up beyond Intel quite recently (about a year ago) and it takes time to develop compatible chipsets and I think there is now a third party who gets to decide about the future of Thunderbolt development and they will be the ones to decide on the standards specifications, it may even be rolled into the USB consortium for all I know etc

Hope this was helpful

 

[Pro7913]

Well with each version of Thunderbolt they have increased its speed. And those speed increases have traditionally been tied to the PCIe specification available at the time except with the move from Thunderbolt 1 to 2 where they merged upstream and downstream channels so that the bandwidth can be dynamically assigned.

So it went like this:
Thunderbolt 1: 10Gb/s up, 10Gb/s down. PCIe 2.0 x4
Thunderbolt 2: 20Gb/s up or down but not at the same time. PCIe 2.0 x4
Thunderbolt 3: 40Gb/s up or down but not at the same time. PCIe 3.0 x4

So the next Thunderbolt specification will most likely be:

Thunderbolt 4: 80Gb/s up or down but not at the same time. PCIe 4.0 x4

There's not really much they can do with the standard beyond increasing its speed at this point. It can already deliver 100 Watts of power, it's already hot-pluggable, it has a very robust and interchangeable connector, it's extremely low latency.

AMD already is shipping PCIe 4.0 equipped processors today (Ryzen 3000, Threadripper 3 and EPYC all support this) but the Thunderbolt standard was only opened up beyond Intel quite recently (about a year ago) and it takes time to develop compatible chipsets and I think there is now a third party who gets to decide about the future of Thunderbolt development and they will be the ones to decide on the standards specifications, it may even be rolled into the USB consortium for all I know etc

Hope this was helpful

Wait, why can't TB3 use 16 lanes instead of 4?

 

[Quu]

Wait, why can't TB3 use 16 lanes instead of 4?

It would require a lot more pins in the connector if they did that. The cables would need to be 4x as thick at a minimum, there would also be problems with crosstalk from all the wires within the cable so it would need a lot more insulation against interference both internally and externally. In addition, the power consumption would be higher, they would require a lot more traces on the motherboard and the CPU's would need a lot more PCIe lanes.

At the moment Intels main CPU's for laptops and mainstream desktops (think the non-Pro iMac, Mac Mini, MacBook Pro etc) all only have 16 PCIe 3.0 lanes from the CPU directly and then the equivalent of a further x4 PCIe lanes between the CPU and the PCH (Platform Controller Hub) called the DMI Bus. The PCH then provides a breakout of more PCIe lanes but there is a bottleneck of that x4 link between the PCH and the CPU.

So if we take for example the Core i9 9900K. Intels current highest end Mainstream desktop CPU which has 8 CPU cores. It only has 16 PCIe 3.0 lanes. Then the PCH on the motherboard provides an extra 24 PCIe 3.0 lanes. However those 24 lanes from the PCH can only communicate to the CPU (if they need to) through the equivalent of 4 PCIe lanes.

So you see the problem with Thunderbolt 3 if it were to use more than 4 lanes it would be starved for bandwidth if it has to go through the CPU for any reason as Apple already dedicates the 16 PCIe lanes from the CPU to graphics in all their Macs that use these Mainstream/Laptop processors.

All the other things on the Mac use the other PCIe lanes from the PCH including their superfast storage. Sound, Networking (WiFi, Ethernet) etc - There's only 4GB/s to play with between the PCH and CPU and it's already oversubscribed on most Macs if you were to use the Thunderbolt 3 ports to their full potential and the SSD at the same time also at its maximum throughput.

This isn't a problem on the Mac Pro and iMac Pro as those processors have something like 44 to 68 PCIe lanes directly from the CPU and more from their PCH as-well.

 

[srgz]

I know this is an old thread but to be clear here TB4 does not increase the speed at all from TB3 as QUU claimed

 

[Quu]

Indeed. When I made my post originally about Thunderbolt 4 likely being 80Gb/ps and requiring PCIe 4.0 this was prior to the Thunderbolt 4 announcement by Intel which sadly is still PCIe 3.0 and so restricted to the same 40Gb/ps as Thunderbolt 3.

I suspect this is due to no currently shipping Intel processor having PCIe 4.0 capability. Perhaps Thunderbolt 5 will increase the bandwidth instead.

 

[MonkeyButt]

Late to this thread but I figured I'd provide an update for future visitors:

Starting from September of 2020 all Intel processors ship with PCIe Gen 4; this is for low and high power laptops along with desktop processors. The mobile variants all have TB4 controllers built into them (this has been a thing since 2019 for the lower power laptop parts, including the current Intel Macbook Pro 13) but still require retimers. As of today, Intel's CCG exec tweeted and quickly deleted https://www.anandtech.com/show/1685...bolt-5-photo-80-gbps-and-pam3-then-deletes-it) an image from their TB lab in Israel of an 80G TB part coming up (TB5). Given development timelines, it seems safe to say that TB5 should be coming in either late 2022 or the early part of 2023.