Do the M5 models have the same size SSD as your M4? Sometimes doubling the size can double the data rate.
Apple Silicon doesn't use PCIe for its SSD, (I/O Registry describes the "Physical Interconnect" as "Apple Fabric" which is not PCIe) but I guess the change you see could be like switching from PCIe gen 3 to PCIe gen 4 (4 lanes), or switching from gen 4 to gen 5 (2 lanes). If it were a single lane, then it would be like switching from PCIe gen 5 to gen 6.
Mac Pro had slots with up to 16 lanes. MacPro2,1 had PCIe gen 1 slots. MacPro3,1 had PCIe gen 2 slots. MacPro7,1 had PCIe gen 3 slots. MacPro8,1 (Apple Silicon) had PCIe gen 4 slots. Each generation doubles the bandwidth of the slot.
Code:
| | +-o ans@19600000 <class IORegistryEntry:IOService:AppleARMIODevice>
| | | +-o AppleASCWrapV6 <class IORegistryEntry:IOService:IOSlaveCPU:AppleIOP:AppleA7IOP:AppleASCWrapV6>
| | | +-o iop-ans-nub <class IORegistryEntry:IOService:AppleA7IOPNub>
| | | | +-o RTBuddy(ANS2) <class IORegistryEntry:IOService:IOSlaveProcessor:RTBuddy>
| | | | +-o RTBuddyIOReportingEndpoint <class IORegistryEntry:IOService:RTBuddyBuiltinEndpoint:RTBuddyIOReportingEndpoint>
| | | | +-o RTBuddyTraceKitEndpoint <class IORegistryEntry:IOService:RTBuddyBuiltinEndpoint:RTBuddyTraceKitEndpoint>
| | | | +-o ANS2Endpoint1 <class IORegistryEntry:IOService:RTBuddyEndpointService>
| | | | +-o RTBuddyService <class IORegistryEntry:IOService:RTBuddyService>
| | | | | +-o AppleANS3CGv2Controller <class IORegistryEntry:IOService:IONVMeController:AppleNVMeController:AppleEmbeddedNVMeController:AppleANS2NVMeController:AppleANS2CGv2Controller:AppleANS3CGv2Controller>
| | | | | +-o AppleEmbeddedNVMeTemperatureSensor <class IORegistryEntry:IOService:IOHIDEventService:AppleEmbeddedHIDEventService:AppleEmbeddedNVMeTemperatureSensor>
| | | | | | +-o IOHIDEventServiceUserClient <class IORegistryEntry:IOService:IOUserClient:IOUserClient2022:IOHIDEventServiceUserClient>
| | | | | +-o NS_01@1 <class IORegistryEntry:IOService:IOBlockStorageDevice:IONVMeBlockStorageDevice:IOEmbeddedNVMeBlockDevice>
| | | | | | +-o IOBlockStorageDriver <class IORegistryEntry:IOService:IOStorage:IOBlockStorageDriver>
| | | | | | +-o APPLE SSD AP2048Z Media <class IORegistryEntry:IOService:IOStorage:IOMedia>
PCIe devices have link width and link rate stored in a property in the I/O Registry. I don't know if Apple's Apple Silicon SSD has any property like that.
I've attached ioreg info from M5 Max MacBook Pro and M4 Max Studio. M5 Max has 2 TB and M4 Max has 1 TB so I guess it's not a perfect comparison.
M5 Max adds a
"High Throughput Options" = 1 property that M4 Max doesn't have. I don't know what "High Throughput Options" means. The 1 could be a boolean true value or it could be a flag bit (meaning that the 1 bit is an unknown option and the other bits in the value may represent other unknown options).