3nm Chips From Apple Supplier TSMC to Enter Mass Production This Week

[Boil]

Well, another big difference was RAM. The A series has its RAM in the SoC. The M series has it on the package, to the side of the SoC. This allows the M1 in the iPad to offer 8 and 16 GiB RAM configs.

RAM has always been "on-package", not "in-die"...

Go look at all the various iFixit teardowns of iPhones & iPads thru the years, they clearly mark the RAM which is on-package, not in-die...

The reason the M-series SoCs support more RAM is because they have more memory controllers, therefore more memory channels, therefore more RAM capacity...

 

[chucker23n1]

RAM has always been "on-package", not "in-die"...

Go look at all the various iFixit teardowns of iPhones & iPads thru the years, they clearly mark the RAM which is on-package, not in-die...

A series layer it underneath the SoC. M series place it next to it.

The reason the M-series SoCs support more RAM is because they have more memory controllers, therefore more memory channels, therefore more RAM capacity...

That’s kind of my point? Having a beefier memory controller is a key way in which the iPad’s M1 isn’t the same as a hypothetical A14X.

 

[Boil]

A series layer it underneath the SoC. M series place it next to it.

Again, look at the pics for yourself, RAM on-package next to the SoC; not in-die, nor under the die (which would be the backside of the PCB)...

That’s kind of my point? Having a beefier memory controller is a key way in which the iPad’s M1 isn’t the same as a hypothetical A14X.

How can that be your point when you did not say anything about a beefier memory controller at all...?

 

[name99]

Again, look at the pics for yourself, RAM on-package next to the SoC; not in-die, nor under the die (which would be the backside of the PCB)...



How can that be your point when you did not say anything about a beefier memory controller at all...?

You seem to be fixated on a point whose relevance/importance is not clear to anyone else.

The A15 and earlier had the RAM mounted as PoP. The RAM is mounted on a small organic substrate with wire bonding of the DRAM to the substrate. This scheme has the advantage that it is cheap (because it has been done for years, the machinery is all old and fully depreciated. But it's not optimal in terms of energy because those wire-bonding wires have extra capacitance.

The A12X, M1 and later mount the DRAM directly on the package. No wire bonding, slightly better for energy, also slightly more expensive. The vertical vs horizontal is just a question of convenience and whether you care more about z-height or area, it is not fundamental.

With the A16 we see the A12X/M1 style brought to the iPhone. Details remain unclear (the sites that used to tear apart Apple chips and give photos have mostly stopped doing this for free...). The one public article I know is
https://eetimes.itmedia.co.jp/ee/articles/2210/25/news048.html#utm_term=share_sp (Japanese)
which claims (and shows some terrible quality photos which seem to confirm) that the A16 is no longer using traditional PoP DRAM. Rather it is using something like a vertical version of the A12X/M1 packaging. There's an epoxy glass substrate with DRAM mounted on one side, A16 SoC on the other side, and presumably via's going through the epoxy glass that connect the two. No more PoP wires, so slightly reduced energy per DRAM read/write transaction.

Point is, the choice of vertical vs horizontal is not "essential"; it's based on what's more convenient given the target product. Even the M1 Max and Pro are somewhat different from the M1. The metal stiffener is substantially more robust, and there area lot more capacitors mounted on the package (for better control of rapid changes in current). The M1 Ultra is different again, with the DRAM rather further from the SoC than on Max. (That slightly increases energy, but allows an inner stiffener ring to surround the pair of SoCs, with an outer stiffener ring then around the entire package). Conceivably in future Apple may move all the DRAM for M class, and some of the DRAM for Pro/Max/Ultra class under the package, like A16, to reduce area. Ultimately the choice is likely to be primarily about cost; is the side-by-side mounting slightly cheaper than vertical mounting or slightly more expensive?

 

[theorist9]

"The all-new M2 Ultra in the all-new 18" MacBook Ultra, we think you'll love it...!"

Actually, that would be kind of cool--a true portable workstation. [Not that we'd ever see something like this.]

 

[chucker23n1]

How can that be your point when you did not say anything about a beefier memory controller at all...?

You’re taking things out of context. The question was whether the M1 is a more significant performance boost to the iPad than a hypothetical A14X would’ve been. One argument for that is: it more than doubled the RAM.

(And no, PoP is not “the backside of the PCB”.)

 

[Confused-User]

The A15 and earlier had the RAM mounted as PoP. The RAM is mounted on a small organic substrate with wire bonding of the DRAM to the substrate. This scheme has the advantage that it is cheap (because it has been done for years, the machinery is all old and fully depreciated. But it's not optimal in terms of energy because those wire-bonding wires have extra capacitance.

The A12X, M1 and later mount the DRAM directly on the package. No wire bonding, slightly better for energy, also slightly more expensive. The vertical vs horizontal is just a question of convenience and whether you care more about z-height or area, it is not fundamental.

You really think so? DRAM doesn't generate nearly as much heat as a CPU would, but it does generate some. Wouldn't the thermals from stacking DRAM on top of the chip be enough of a negative to avoid doing that, at least for your high-performance chips (Pro and up)?

I guess the counterargument is that it's already being done with caches (AMD's "3D" extra-cache CPUs) and various HPC setups using HBM. So maybe it really isn't a big deal, but I have to admit I've never understood why. I'd naively thought that getting a heat sink in as close to direct contact as possible with the CPU hotspots would be a top priority, though perhaps the RAM is so thin that it has almost no impact on thermal transmission? Do you know the answer?

 

[Gudi]

The reason the M-series SoCs support more RAM is because they have more memory controllers, therefore more memory channels, therefore more RAM capacity...

They have also more cpu/gpu cores, which means they crunch more numbers and can make use of all those extra memory. It makes no sense to pack an M1 Ultra with only 8GB RAM or an M1 with more than 64GB. The amount of memory chips and memory controllers is tailored to the performance of the chip itself.

You shall not doubt the amount of memory Apple built into your system! 😇

 

[BorisDG]

Well, another big difference was RAM. The A series has its RAM in the SoC. The M series has it on the package, to the side of the SoC. This allows the M1 in the iPad to offer 8 and 16 GiB RAM configs.

All are using PoP technique. The real CPU of A is under the TOP black which is the RAM. Watch Dr. Ben changing the RAM of A chips.

 

[MrDerby01]

When a company makes a chip cpu or gpu.. Am I correct the chips are smaller until a they put a protective cover around it?

 

[name99]

You really think so? DRAM doesn't generate nearly as much heat as a CPU would, but it does generate some. Wouldn't the thermals from stacking DRAM on top of the chip be enough of a negative to avoid doing that, at least for your high-performance chips (Pro and up)?

I guess the counterargument is that it's already being done with caches (AMD's "3D" extra-cache CPUs) and various HPC setups using HBM. So maybe it really isn't a big deal, but I have to admit I've never understood why. I'd naively thought that getting a heat sink in as close to direct contact as possible with the CPU hotspots would be a top priority, though perhaps the RAM is so thin that it has almost no impact on thermal transmission? Do you know the answer?

Gee, it's almost as though Apple's obsession with low power rather than GHz uber alles actually has some real on-going advantages...
The fact that Intel cannot do this for thermal reasons does not mean that Apple cannot.

 

[name99]

When a company makes a chip cpu or gpu.. Am I correct the chips are smaller until a they put a protective cover around it?

Yes, though the details differ substantially, as does the extent to which the size increases.
The package may also be a lot larger than you expected to accommodate bumps/pins to connect the package to the motherboard; in that case the SoC will sit on an RDL (redistribution layer) that spreads out the wiring from the tiny bumps at the bottom of the SoC to larger bumps across the bottom of the package.
A third factor that may determine the overall package size is capacitors. The more rapidly current may change in the SoC, the more capacitors are needed, and large capacitors (and a few inductors) may be spread all over the package anywhere there is free space to deal with this.

You can see many details of this, and how the packaging has changed across Apple generations, in my packaging pdf:
Download volume 5 from https://github.com/name99-org/AArch64-Explore

 

[dgdosen]

You seem to be fixated on a point whose relevance/importance is not clear to anyone else.

The A15 and earlier had the RAM mounted as PoP. The RAM is mounted on a small organic substrate with wire bonding of the DRAM to the substrate. This scheme has the advantage that it is cheap (because it has been done for years, the machinery is all old and fully depreciated. But it's not optimal in terms of energy because those wire-bonding wires have extra capacitance.

The A12X, M1 and later mount the DRAM directly on the package. No wire bonding, slightly better for energy, also slightly more expensive. The vertical vs horizontal is just a question of convenience and whether you care more about z-height or area, it is not fundamental.

With the A16 we see the A12X/M1 style brought to the iPhone. Details remain unclear (the sites that used to tear apart Apple chips and give photos have mostly stopped doing this for free...). The one public article I know is
https://eetimes.itmedia.co.jp/ee/articles/2210/25/news048.html#utm_term=share_sp (Japanese)
which claims (and shows some terrible quality photos which seem to confirm) that the A16 is no longer using traditional PoP DRAM. Rather it is using something like a vertical version of the A12X/M1 packaging. There's an epoxy glass substrate with DRAM mounted on one side, A16 SoC on the other side, and presumably via's going through the epoxy glass that connect the two. No more PoP wires, so slightly reduced energy per DRAM read/write transaction.

Point is, the choice of vertical vs horizontal is not "essential"; it's based on what's more convenient given the target product. Even the M1 Max and Pro are somewhat different from the M1. The metal stiffener is substantially more robust, and there area lot more capacitors mounted on the package (for better control of rapid changes in current). The M1 Ultra is different again, with the DRAM rather further from the SoC than on Max. (That slightly increases energy, but allows an inner stiffener ring to surround the pair of SoCs, with an outer stiffener ring then around the entire package). Conceivably in future Apple may move all the DRAM for M class, and some of the DRAM for Pro/Max/Ultra class under the package, like A16, to reduce area. Ultimately the choice is likely to be primarily about cost; is the side-by-side mounting slightly cheaper than vertical mounting or slightly more expensive?

What's your perspective on Apple using "TSMC 3D Fabric" sooner or later when moving more vertical? If Apple is a close partner on using new nodes, might they be a close partner on 3D Fabric?

 

[BorisDG]

Actually that's the article.

 

[deconstruct60]

What's your perspective on Apple using "TSMC 3D Fabric" sooner or later when moving more vertical? If Apple is a close partner on using new nodes, might they be a close partner on 3D Fabric?

' sooner or later' ? Apple already uses Info-LSI for the baseline technology of "UltraFusion". They have already shipped 10's of thousands of the product already.

https://www.tsmc.com/english/dedicatedFoundry/oip/3dfabric_alliance

Pretty good chance Apple isn't didn't do all of the UltraFusion work by hand so at least one of the EDA tool vendors in the alliance probably has a role in the design process for that too.

 

[deconstruct60]

I guess the counterargument is that it's already being done with caches (AMD's "3D" extra-cache CPUs) and various HPC setups using HBM. So maybe it really isn't a big deal, but I have to admit I've never understood why. I'd naively thought that getting a heat sink in as close to direct contact as possible with the CPU hotspots would be a top priority, though perhaps the RAM is so thin that it has almost no impact on thermal transmission? Do you know the answer?

AMD's 3D cache is layered on top of just the cache on the die; not the 'CPU' cores. Are not particularly 'loosing' a direct thermal transmission path from the cores dissipation and the package's heat spreader.

Welcome to AMD

AMD delivers leadership high-performance and adaptive computing solutions to advance data center AI, AI PCs, intelligent edge devices, gaming, & beyond.

www.amd.com

The computational cores are on the outer 1/4 of the die. The shared cache memory is in the middle.
So the memory is stacked. ( many LPDDR and DDR memory packages have stacked RAM dies also. Different stacking mechanism but the thermal of putting one on top of the other is more same than different). There is a 'filler' that they have to put over the outer 1/4's (cores). But that filler doesn't have to be a thermal barrier.

If make the cache on the die lots smaller and/or the whole die gets smaller ( much smaller cores and/or number of heavy/dense logic cores ) then could start to run into issues.


HBM is stacked RAM dies also. But so far those are mainly just horizontal placements on the same die. Can use a 3D interposer to cut down on the memory controller fan out space from the 'main' die, but not doing TSVs out the bottom of RAM stack directly into a 'compute' die.

Apple's semi-custom "poor man's HBM" LPPPDR5 packages are already 3D . Putting that even 'deeper' under (or over) something else) seems a stretch as it is already '3D' . And the SRAM on die caches are not going to get smaller. N3's is slightly smaller than N5 and N3E is the same size (pragmatically no shrink at all).

 

[deconstruct60]

According to the new report by DigiTimes, TSMC will start mass production of its next-generation 3nm chip process on Thursday, December 29, in line with reports from earlier in the year that said 3nm mass production would begin later in 2022. From the report:

TSMC is scheduled to hold a ceremony at Fab 18 at the Southern Taiwan Science Park (STSP) on December 29 to mark the start of commercial production of chips using 3nm process technology. The pure-play foundry will also detail plans to expand 3nm chip production at the fab, according to sources at semiconductor equipment companies

TSMC is going to have a dog and pony show about 'blank' wafers going into a multiple week long production process. if this was a 'car' plant the big press dog and pony show would be about the first finished car that comes off the "running at full speed" production line.

You would think they would want to demonstrate finished wafers coming out quickly (or at least relatively quickly ). Not blank ones aren't ready yet. Sure they could whip out some of the 'at risk' produced wafer ( it isn't like they haven't been processing lots of N3 wafers already. They have probably have been making something for someone . It just haven't been 'tagged' " High volume Manufacturing" status. ).


That would largely match up with the quarterly report earlier in the year where TSMC said there would be a modest amount of money coming for N3 wafer sales in Q4 , but not enough to make a significant difference, but substantative money would flow in Q1. If just starting 'blank' wafers now , hard to see how there would be a deep impact on Q1 numbers as most of Q1 would still be waiting for the wafers to finish.

N3 'throughput' (how long it takes to gestate) is part of the issue.

 

[AppleFan1998]

Hoping for a great M2 Mac Mini with lots of ram available like the studio..

 

[Boil]

Hoping for a great M2 Mac Mini with lots of ram available like the studio..

Base Mn SoC will never have as much RAM as Mn Max/Ultra SoCs...

As we see with the 13" MBA/MBP laptops, the M2 SoC will go up to 24GB of RAM...

Now, if Apple ever decides to give us a Mac mini powered by the M2 Pro SoC, then we could see up to 48GB of RAM...

 

[binarysmurf]

Not sure if anyone can answer this, but will it be safe installing a Bootcamp partition with Windows 10 while running Ventura with OCLP? I don't want to wipe my macOS install while installing Windows 10. 😳