Originally posted by gbojim
OK I can help with this one. Sorry in advance for the long post.
CPUs have different types of busses: data, address, internal and external.
The internal data bus determines how much data can be processed during the execution of a single command - eg adding 2 numbers. If you can add 2 64 bit numbers, you get twice the performance as adding 2 32 bit numbers.
However, not all data is 64 bits. For example, keystrokes are represented as 16 bit data, so even 32 bit capacity is overkill for that. So, unless you actually have 64 bit data that you are manipulating, increasing the data bus does not help you.
According to the Book E spec which defines the G5, integer processing units are increasing from 32 to 64 bits - making the G5 64 bit data since integer units are normally used to determine the data size of the processor. The floating point processing units remain at 64 bit - same as the G4.
Also, you cannot combine data streams. So, when the G5 comes out, any programs that are designed and compiled for 32 bit will use half of the data bandwidth available according to Book E, and you won't be able to run 2 32 bit data streams at a time to take advantage of the unused capacity.
The virtual address space for G5 is moving from 32 to 64 bits. This means that any one program running on the G5 will be able to address up to 2^64 bytes of memory (I don't know what to compare that to because it is soooo huge). The OS will determine how much of the address space user apps can use. There are very few apps even today that really need and can take advantage of that, which is why the Alpha did not do as well as DEC hoped it would.
The external data bus determines how much info is transferred across the memory bus when loaded or stored. The G4 is 64 bit (Maxbus), so it loads 2x as much data as is requested during one load command - same as Intel does it on some of it's processors. The theory is that the next info requested will be right beside what you are requesting now, so it will be preloaded in cache when actaully required. If you have good compilers, this works great. I haven't seen any info as to what bus will be used on the G5.
The external address bus determines how much memory you can physically talk to on the memory bus. The G4 is 36 bit, so although any one program can only address 4GB (32 bit), you could actually have 64GB on the system. I haven't seem any info about what is happening with the G5 in this area.
Finally, the dual core issue. You are right in that 2 cores means 2 complete CPUs on 1 die. This is blazingly fast if you have a large cache running at or near the clock speed of the CPU because the communications between the processors takes place at CPU speed. The biggest issue in this area is keeping the CPUs fed with data because of the delay in accessing main memory to feed the cache.
Hope this helps. If I confused anyone, let me know and I'll try to fix it.
