Um, no, it has nothing to do with "porting skills".
The gcc compiler in general does a poor job of optimizing code for the G4 relative to, say, MSVC's compiler optimizing for the P4.
Personally, I've gone through many long performance-optimization sessions with high-level Apple engineers. We've been able to get sometimes 3-5% performance improvement through our Sampler/optimize rounds, which they said is fairly low because my code tends to follow the G4-programming guidelines as it is (ie, reduce cache misses above all else, compute static variables instead of pull them from memory, etc). in all, we've pulled about a 50% performance improvement out of our hats, which isn't bad.
We then copied the improved code over to the Windows compiler, ran through the same tests, and what do you think we found? In all cases (except one), a 3-5% improvement on the OS X side corresponded to a 5-8% improvement on Windows. The overall performance gain on Windows was over 100% (ie, twice as much work done in the same amount of time).
Before these improvements, the G4 and P3 were neck-and-neck for overall performance by clock cycle. Afterwards a 500MHz P3 runs faster than a 733MHz G4.
About my application: there are a lot of unavoidable cache misses as we work with a complex and inter-related data set. SIMD (Altivec or SSE, take your pick) cannot be used in any manner (at least, not that I could find, and not that our Apple friend could find either).
Yes, this is anectdotal, and, no, I'm not going to drop names. But take it from me, it's not "poor porting" that is the cause of the G4 performing piss-poor compared to Intel's line. It is the overall architecture of the chip.
