AppliedVisual said:It will come, just not with the initial production models. With the quad-core chips, Intel is already running into FSB bandwidth issues as it is. The Clovertowns are essentially dual Woodcrest CPUs stuck on the same die, sharing the same FSB and communication between the first duo-core CPU and the second duo-core CPU on that die must travel onto the FSB and into the other CPU. Between the two cores that are linked directly, data sharing can be handled through the L1 cache. So, depending on your application, the 8-core may be no better than a 4-core system -- if what your'e doing is already maxing out your CPU bus bandwidth. Somwhere down the road as Intel shifts to its 45nm production process and fully integrates all 4 cores on a single CPU (and later, 8 cores on die), we will see massive improvements in inter-core bandwidth. They will have to step-up on the FSB bandwidth though... Possibly by increasing the MHz, but more than likely we'll see some of that combined with increasing the width of the data path and possibly using multiple parallel FSB designs. ...Going to be interesting, that's for sure. And with Intel's new process and the plans for continuously jamming more cores onto a die at higher speeds, I think we're in for a real ride over the next 5 years or so.
Absolutely agree. It must be exciting to be an EE working on this stuff right now. So many options to explore. How would you design a memory bus which would be dynamic enough to adjust for a doubling of processors? If you had a fixed, known number of processors, the design is straight-forward. But, the new multi-core design is not something they have had to deal with before. I wonder how they will do it?