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Perhaps should you create a new thread asking people to do it honestly

Oh and if you do,I'd be thankful if u could lemme know about it buddy :)

Have done so, let’s see if it gets some interest!

 
Thanks for the insight man !
What exactly is dynamic power ? And on average how much does leakage power represents compared to the 10c fly enabled variant would u say ?
You said it's a big chunk ,but I'm curious to know what you mean by that.somethinf like 50% of the power,or closer to 90% lol

Leakage power in advanced nodes can easily be 50% of the total power dissipation. Dynamic power is the power consumed when the CMOS gates (switches) are actually switching, using the famous CV^2f formula. The size of the circuit is essentially C, f is the clock frequency of the design, and V is the voltage applied to the gates. The gate voltage has been getting smaller as the transistor size (e.g. 5 nanometer) has been dropping. If the clock is not switching or the voltage to the circuit is shut off, then the dynamic power drops to zero. Leakage power can only be shut off if the voltage applied to the circuit drops to zero (e.g. a switched-power design, very common in low-power, battery powered devices).

Hope that helps.
 
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