Last I checked, the Sandy Bridge EN parts where LGA135
6 (not 1355, sorry

), not LGA2011 (EP versions for sure). It's no longer listed in the wiki page however (
32nm section), so that information was either wrong, or Intel may have requested it be removed.

There's no socket information for the EN versions (to be marketed as Xeon E5 it seems; Xeon E7 for the EP, and a single processor server chip as the Xeon E3), and the different pics have different information (one lists a 4x channel memory controller, another,
Server section, still lists it as 3x channel (which is what it was listed at previously).
It was nice, clean, and easy to understand. Now, not so much.
At any rate,
here's a source (.pdf file) of the socket data (LGA 2011, LGA 1356, and LGA 1155). The reduced pin count is due to 1x QPI lane (vs. 2x), PCIe lanes (24 instead of 40), and one less memory channel (3x vs. 4x in the EP's).