With all the talk around 5nm vs 3nm, not many people mentioned the idea of 4nm for the next Apple Silicon chips. Based on my limited reading, a 6% die shrink is achieved moving from 5nm to "4nm". No, the math doesn't add up, it should be 20% smaller of course, but this is 4nm in name only and is actually a further derivative of 5nm - correct me if I am wrong?
TSMC calls them N5 , N4 , N4P , N3 , N3E . It is largely the tech press can keeps stripping off the 'N' (node) and slapping the 'nm' suffix on it. It is a multidimensional issues that are being mapped to a single number. That's why putting a standard measurement unit on it is kind of goofy and why Intel and TSMC have basically stopped if pay addition to their formal announcements.
So dividing the numbers leads to a lot of nothing ( 20% ).
Here are two TSMC's N4P . Yes there is briefly a "5nm-family" in here , but they are synthesizing the "nm" there.
N4P
https://pr.tsmc.com/english/news/2874
"... As the third major enhancement of TSMC’s 5nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks ..."
N4X
https://pr.tsmc.com/english/news/2895
" ...
N4X is the first of TSMC’s HPC-focused technology offerings, representing ultimate performance and maximum clock frequencies in the 5-nanometer family. ...
...
...
These HPC features will enable N4X to offer a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. Customers can also draw on the common design rules of the N5 process to accelerate the development of their N4X products.
..."
The basic design rules the implementations have to fit inside of are the same for the original N5. The implementations for the cell libraries are optimized to eek out more performance/power/area benefits .
Even with the design rules being the same there is still some work needed to be done polish off and finish the design. But it is substantially less work if the design rules were not compatible.
That is why they are all in the "5nm-family" but there are substantive changes, but not enough to push it out of the "family".
N4 was already in High Value Manufacturing status this Spring '22. N4P is/was a better candidate if only concerned about performance improvements, but when announced it wasn't suppose to appear until 2H '22 . That makes it too late for the iPhone. However, in recent Quarterly ( JULY 22 ) conference call
" ... With the successful ramp of N5, N4P, N4X, and the upcoming ramp-up of N3, we will expand our customer product portfolio and increase our addressable market. The macroeconomic uncertainty may persist into 2023, our technology leadership will continue to advance and support our growth. ..."
N4X seems like a mistake or 'ramp' means something slightly different here as it was just announced in Dec '21. Not sure why they didn't mention N4 plain as it had already gone HVM.
Some folks dimissed N4 because there was no performance/power gap over N5P. The 6% smaller actually matters though.
A12 84mm2
A13 99mm2
A14 88mm2
A15 107mm2
94% of 107mm2 --> ~100nm
and if the additional camera processor and fixed function additions were a 2-3% addition then the tread-water at still around 107mm2 (instead of even higher).
The 107mm2 die would get between 430-530 dies per 300mm wafer.
At 100mm2 die would get between 474-574 dies per 300mm wafer.
So there is a gap 44 dies. Over 1,000 wafers that is an additional 44,000 dies that you get for 'free' ( presuming N5P and N4 wafer cost approximately the same ). Let's say you were getting the whole 530/wafer on the N5P process. That's 83 extra wafers have to do to catch up to the N4 throughput. At $17K a wafer, that is $1.4M extra money spent per 1,000 wafers just to stick with N5P. If going to do 174K wafers, then saving about $244M . And have also freed up wafers to make other stuff with! So there is an upside.
The M1 Pro is 240mm2. Shaving 6% off that would be slicing off ~14mm2 . Less wafers to print more dies at lower aggregate cost. The volume is a lot lower so it get murkier as to where the breakeven is. There are also few places for the old M1 Pro to go after retirement from the lead MBP 14" M1 . ( on iOS land.. toss into AppleTV, iPad , etc. later. )
At the "Max-like" die size ( 420nm2 ) shaving off 10% ( 42mm2 ) is pretty good. That is like half the size of an iPhone chip per 'Max-like' die over the whole wafer. 20% ( 84mm2) is about a while iPhone die per 'max-die" over the whole wafer. If make a milliong 20% smaller Max-like dies get a million 'free' iphone chips of wafers savings.
Given Apple's website isn't showing off much in the way of performance gains for the new chip, it makes me wonder if there are really any major improvements at all, except for efficiency gains / reduction in power, but at the same clock speeds as the A15.
At least in the USA the price of the iPhone stayed the same. Isn't that an improvement. ( lots of folks in other countries where their currency isn't doing so hot are grumbling. )
Could the M2 Pro/Max adopt this same process? This may be the reason why some rumours existed about them being 3nm, then others saying it will stick to 5nm.
M2 Pro. Maybe. Adding to Mini's to crank up the unit volume would help to make that work better. MBP 14/16" have to deal with the Max's TDP so if there is some thermal creep with more cores/compute that isn't going to be huge problem.
M2 Max .... eh if it was N4P maybe. N4 I suspect doesn't work so hot (or is hot if add enough cores) . If can share costs over the A16 and M2 Pro then it may work. Likely causes some problems for the "double Max-like die" product if trying to keep Info-LSI packagig and goose up the E core and GPU core counts plus put in some camera/video processor improvements. The Max is really kind of "too chubby" to be a 'chiplet'. Apple may be dumping Info-LSI tech in the dual chip package anyway because it isn't going to scale to 4 chubby 'chiplets'. If going to share R&D costs across 2 and 4 packages then decent chance want to be using same tech ( even if it increases costs for the 2 chip set ups. Just pass that along to customers. ) . Apple could go this route. I don't think this path will help desktop customer pocketbooks though ( price creep).
If it is N4 , then I wouldn't be surprised if they chopped off the UltraFusion part. It was a laptop only M2 Max. Couldn't be used in a desktop multiple chip package set up at al. ( like the original pictures they put up for the Max when it launched. Only this time, it not photoshopped die photo. )
