Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
Aren't these all supposed to be the same base chip as the other AMD GPUs? If so, driver implementation shouldn't be much of a challenge since it would use the same driver. Just updating code to properly recognize the hardware ID.
 
Interesting find. Yes, there is now a preliminary Navi driver in macOS. It lists a single device ID, 0x7310. That appears to be the Navi 10 Alpha engineering sample.
 
  • Like
Reactions: itdk92
Aren't these all supposed to be the same base chip as the other AMD GPUs? If so, driver implementation shouldn't be much of a challenge since it would use the same driver. Just updating code to properly recognize the hardware ID.

No - Navi is a different architecture.
 
http://www.freepatentsonline.com/20180121386.pdf
http://www.freepatentsonline.com/20180144435.pdf
Those are patents linked to Navi GPU architecture, which were released in May, last year.

And this has appeared just in the December:
http://www.freepatentsonline.com/20180357064.pdf

Only last patent is so ground breaking change that would make Navi vastly different from previous versions of GCN.

Also, it appears that you can implement each of those patents regardless of each other. But they will not funtion properly as they should. It is combined together tech, which should have been designed together, and implemented together, because it is straight up affecting GPU execution pipeline on the lowest levels.
 

>... There have been rumors that Navi will be the last GCN-based architecture. These patent applications add some credibility to the rumors, though obviously we will have to wait and see what transpires.
Read more at https://hothardware.com/news/amd-pa...pu-performance-gap-nvidia#b6T1ldTgSrttylWC.99 ..."

Rumors I've seen is that Navi isn't GCN. That the Vega baseline is the last iteration. Akin to Intel old Tick-Tock sequence where 'Vega 20' is the tick (process shrink 7nm ) and Navi was the tock ( significant microarch change). that would give AMD a snapshot of logic they "know" on 7nm before they go to broad full scale production on a new architecture ( and some of the knowledge about glitches associated with the shrink could have some possibility of being folded back into the new micro arch. )


Because a new micro arch a relatively short term "bottom to top" (or vice versa) rollout is pretty unlikely. Lots of software/drivers/etc to catch up to the move. (iterating to a another support level tier like macOS even longer still) So "Vega" (10/20) getting replaced soon is a probably not in the Mac Pro ( and iMac Pro ) context.

Apple putting Navi into an MBP 15" or iMac ( were replacing Polaris class products) seems far more likely in 2019 than anything at the top of the desktop spectrum in the Mac space.
 
>... There have been rumors that Navi will be the last GCN-based architecture. These patent applications add some credibility to the rumors, though obviously we will have to wait and see what transpires.
Read more at https://hothardware.com/news/amd-pa...pu-performance-gap-nvidia#b6T1ldTgSrttylWC.99 ..."

Rumors I've seen is that Navi isn't GCN. That the Vega baseline is the last iteration. Akin to Intel old Tick-Tock sequence where 'Vega 20' is the tick (process shrink 7nm ) and Navi was the tock ( significant microarch change). that would give AMD a snapshot of logic they "know" on 7nm before they go to broad full scale production on a new architecture ( and some of the knowledge about glitches associated with the shrink could have some possibility of being folded back into the new micro arch. )


Because a new micro arch a relatively short term "bottom to top" (or vice versa) rollout is pretty unlikely. Lots of software/drivers/etc to catch up to the move. (iterating to a another support level tier like macOS even longer still) So "Vega" (10/20) getting replaced soon is a probably not in the Mac Pro ( and iMac Pro ) context.

Apple putting Navi into an MBP 15" or iMac ( were replacing Polaris class products) seems far more likely in 2019 than anything at the top of the desktop spectrum in the Mac space.

Navi is part of GCN architecture base on the AMD CPU roadmap. After 2020, they will have a whole new architecture for CPU. You can check Google.
 
Navi is part of GCN architecture base on the AMD CPU roadmap. After 2020, they will have a whole new architecture for CPU. You can check Google.
There are well informed people who say that Navi is not entirely GCN and it is, and will be, vastly different in some way, than previous versions of GCN.

ONLY changes of the scale mentioned in the patent above could put some truth to this rumor.

https://twitter.com/KOMACHI_ENSAKA/status/1072559060631863300
The guy mentioned by Komachi is famous for his previous AMD correct leaks(Polaris 30, on 12 nm process(RX 590). He claims Navi is vastly different than previous gen's of GCN.

He also says his sources tout that Navi is different than previous versions of GCN.

Also, remember that change in CU number may simply mean, that there is less ALUs/CU/256 KB Register File. For example rumor has it that Navi 12 is 40 CU chip. It may mean, that we are talking actually about... 1280 Cores instead of 2560, like it would be in previous versions. Those 1280 cores would have basically the same throughput and performance, as those 2560 cores.

Thats why Coreteks source can be corect about that 96 CU count. It will simply mean we are looking at 3072 core GPU.

Everything here is speculation, so far.

Lastly. Last rumors, from AdoredTV, say that Navi GPus are actually smaller than Polaris GPUs, that are meant to replace. So less than 132 mm2, and less than 232 mm2. Both are supposed to have GDDR6. Which even in 128 bit memory bus it will mean up to 8 GB's of VRAM.
 
Last edited:
Navi is part of GCN architecture base on the AMD CPU roadmap. After 2020, they will have a whole new architecture for CPU. You can check Google.

Checked. Didn't find anything creditible. There is certainly some noise kicked off by WCCF tech and few other sites in echo chamber mode, but didn't find anything substantive in AMD's materials.

In fact, 2016 Roadmap

Roadmap2_575px.jpg


https://www.anandtech.com/show/10145/amd-unveils-gpu-architecture-roadmap-after-polaris-comes-vega

Navi is targeting scalability. Which given GCN's 4096 cap on CUs would seem likely to be a scalability problem they'd be looking to actually solve. Perhaps that is a different kind of scalability other than CU count, but it is seriously point to not being "same stuff different day". Similar with aspect with doing a major shift in Memory management and/or bandwidth. Same basic cache mechanism on brand new memory subsystem doesn't really mesh well.


2017 .....

gpuroadmap_575px.png


https://www.anandtech.com/show/11404/amd-updates-gpu-architecture-roadmap-after-navi-comes-next-gen

Somehow Navi is cranking up the performance increase substantively but making no basic changes to micro arch? Errrrrrrr, does that make sense? Also note here that "Navi" is on 7nm and Vega is only on 14nm and 14nm+. The part where the WCCF noise creep is that leap that somehow AMD is purely 100% talking about "code words" for the first two columns there and then widely switch aways away from code words to specifically talk about arch implementation in the third column of the same graph. That would either be pretty horrible graphic presentation methodology or is it is huge bit of wishful handwaving. I pretty much think it is the latter.

Stuff like "Polaris" , "Vega" "Navi" are typically code names vetted for external use. Things like "Butthead Astronomer" or something that means "Your mom smells like a donkey" in some foreign language tend not to be good external/public code names. "Next Gen" in the above context is far more likely to be "Code name that we have come up with yet" rather than some huge leap into the underlying code development.


Also note that in other 2018 rumors the primary driver of Navi was the gaming console vendor who typically pick something stick with it for 3-4 years. Are they really going to pick a basic micro arch foundation that will be 100% off the track of picking up perf-per-watt updates on future process shrink iterations? Would that be a good or bad idea?



In 2018 ( this about the hand waving period of time where WCCF related stuff starts getting traction of Navi being yet another rehash because Raju left and AMD is completely off track crowd grew over the course of the year ).

gpu_to_2020_575px.jpg

https://www.anandtech.com/show/1223...ealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm


Again the notion that these are a list of microarch consistency is is kind of goofy. If Vega 14nm is GCN5 then VEGA 7hm is almost certainly pragmatically GCN6. It is a tweak. The instruction set changed. The caches changed. Number of memory controllers changed. In fact some of things on the earlier roadmaps that were nominally Navi got weaved in. So did AMD retag 2016 Navi as Vega 20. ( if going from 2-4 HBM paths and 2nd generation HBMv2 implementations was "next gen memory) then perhaps so. The previous year it wasn't even there......... Hmmmm. ( so the GCN just shrunk to 7nm is still Navi in the above diagram? Really? )


However, all of the "Next-Gen" is still most likely a placeholder code name that doesn't exist yet externally. 7nm+ being a process shrink ( likely a move from DUV and some extra step to a more "7nm" clean EUV process ) even more so. Take Navi and shrink the process. Bring up a radical new arch on a process that you have zero familiarity with isn't a particularly good idea. Any stumble on that and Nvidia will pummel them. ( Apple gets away with it a bit on the A-series because they are so far ahead in their narow niche they can afford to stumble and have a giant cash horde to pay for most lightweight screw up. (crappy yields .... just raise prices. ) ). AMD with a huge stumble is a mistake they can't afford. Intel getting into the discrete game even less so.
[doublepost=1548449084][/doublepost]
...
Lastly. Last rumors, from AdoredTV, say that Navi GPus are actually smaller than Polaris GPUs, that are meant to replace. So less than 132 mm2, and less than 232 mm2. Both are supposed to have GDDR6. Which even in 128 bit memory bus it will mean up to 8 GB's of VRAM.

If the number of functional units ( cores , cache , memory controllers , etc. ) is approximately the same then going from 14nm to 7nm would highly likely lead to a smaller implementation. Even if bump the cache up a bit , they'd probably still see a size shrink a bit. It doesn't necessarily point to a quantum leap due to doing twice as much work with 1/2 ( or 3/4) the cores as before. That too would help but the fact don't have 'apple to apples" on fab process tech is going to highly muddy the waters as to what is actually driving size changes.
 
Last edited:
There are well informed people who say that Navi is not entirely GCN and it is, and will be, vastly different in some way, than previous versions of GCN.

ONLY changes of the scale mentioned in the patent above could put some truth to this rumor.

https://twitter.com/KOMACHI_ENSAKA/status/1072559060631863300
The guy mentioned by Komachi is famous for his previous AMD correct leaks(Polaris 30, on 12 nm process(RX 590). He claims Navi is vastly different than previous gen's of GCN.

He also says his sources tout that Navi is different than previous versions of GCN.

Also, remember that change in CU number may simply mean, that there is less ALUs/CU/256 KB Register File. For example rumor has it that Navi 12 is 40 CU chip. It may mean, that we are talking actually about... 1280 Cores instead of 2560, like it would be in previous versions. Those 1280 cores would have basically the same throughput and performance, as those 2560 cores.

Thats why Coreteks source can be corect about that 96 CU count. It will simply mean we are looking at 3072 core GPU.

Everything here is speculation, so far.

Lastly. Last rumors, from AdoredTV, say that Navi GPus are actually smaller than Polaris GPUs, that are meant to replace. So less than 132 mm2, and less than 232 mm2. Both are supposed to have GDDR6. Which even in 128 bit memory bus it will mean up to 8 GB's of VRAM.

Like deconstruct60 said, AMD already showed the roadmap that Navi architecture will be part of GCN architecture.

https://www.overclockersclub.com/news/41365/
https://en.wikipedia.org/wiki/Graphics_Core_Next#Navi
 
Like deconstruct60 said, AMD already showed the roadmap that Navi architecture will be part of GCN architecture.

https://www.overclockersclub.com/news/41365/
https://en.wikipedia.org/wiki/Graphics_Core_Next#Navi

I didn't say that at all. You first overclockerclub is references WCCF's stuff which is probably hand waving. ( saying they have a spotty track record is being modest. )

The wikipedia entry. ... far more likely "echo chamber" stuff. The reference on that entry once again points back to WCCF hocus pocus. Again, largely the same "echo chamber" origin point.

"Next Gen" is far more likely a placeholder for a more specific code word that AMD will come up with later. There is nothing necessarily specifically telegraphed there about micro architecture there much at all. Everything on the right of the graph is a "Next" iteration no matter what the roadmap graph.

Marking GCN specifically is not the primary purpose of those graphs.
 
Last edited:
I do not see any word in those roadmaps that would imply that Navi is GCN based. All I see on ALL OF those roadmaps are word: Graphics Architecture Roadmap, Graphcis Architecture leadership, etc.
 
On the matter of features, it appears that PC Navi GPU architecture lacks completely Ray Tracing Features.

Next gen consoles, on the other hand will have Ray Tracing tech, despite using Navi cores as base.
 

Sigh . some click bait links are not really "your best friend". Googling with no reading comprehension or critical thinking skills is not "your friend".

No clue what that expreview.com thing does for me it takes way to long to load. ( indicative of tons of disco hocus pocus ).

The WCCF post is weak as water. First claims that Navi will be the 6th GCN iteration when it isn't. That Vega 7nm is the 6th. ( not the 5th. There may be some AMD PR or leak that is claiming it is '5" but if add instructions, then that is a next iteration. )

So if 6th was the 'last' and Navi comes after the 6th then ...... ta da ... new foundation iteration.

Was "Vega 20" 100% crystal clear at that point. Perhaps not 100% but there was enough to be somewhat reckless to have promote notion that "Vega 7nm" was purely just a shrink and not another GCN iteration.


Second major flaw

"... We were told that work had already started on the brand new major-architecture before even left, ..."

Right according to the 2016, 2017 , and 2018 roadmaps is Navi. Go and look at the patent filed on dates for the three patents linked in earlier in the thread. (the date on which is published is only relevant in being able to see the completed application. The date filed is more important if this is a patent explicitly being developed for a real product. ) late 2016 , late 2016 , mid 2017. The content of patents is typically worked on many months before they are filed. That puts that research work back in 2015-2016. So was a new arch being worked on before Koduri left in late 2017? Yes. Do these patents' context date about a year earlier than his departure? Yes. Was Navi being worked on a couple of years before his departure? Yes, at least the planning ground work stage for years mark and certainly well in flight by the leaving time. ( it wouldn't be an explicitly named item on a 2016 roadmap if that were not the case).

Getting a significantly different micro-architecture out the door can 3-5 year effort. AMD started in 2014-2015 then 2019 is about on target. We have substantive patents being put together in 2015 and a new named arch coming in 2019. It isn't 100% conclusive but it fits but the timing and the little details that AMD attached to the Navi release on these timelines.

"...AMD has already hinted in its slide deck about the existence of this major architecture. Remember the “Next-Gen” micro-architecture that was listed in their roadmap? Well, its the one and the same. ..."

That's mostly hand waving. I covered that in previous posts. "Next Gen" is far more likely just a placeholder for a name they'll come up with later. It isn't necessarily descriptive of implementation differences from GCN. It comes after Navi is probalby mostly what 'Next' means there.

In fact this comes a relatively shorter after ...

"... and we don’t even have some tantalizing codenames to offer but one thing is for sure, it ".

Right! There is no codename for the next generation so AMD is using the label "Next Gen" . If you supposedly don't have a code name and all AMD wrote down was something else then that something else is pragmatically the code name. Just because it isn't a 'Tantalizing' code name doesn't mean that it is not a code name. "Next Gen" isn't sexy/tantalizing enough so it can't be a code name is 100% rubbish. Just garbage.

Thrid major flaw (hand waving)

"... t is known that this brand new architecture will result in a leap that is at-least as great as the TeraScale to GCN shift. Since the process will be the 7nm+ optimized node ... "

if the new arch is so much better of an implementation why does it require a new process shrink. If have grips on a significantly better arch implementation then should be able to put it onto the a 7nm fab process and still get a major boost. If it is required that get to a shrink to get a boost then the shrink is just as likely playing a major role there; not the arch.
 
Last edited:
Dec, what is even funier, the same WCCFTech site has posted this:

https://wccftech.com/exclusive-first-amd-navi-gpu-will-have-40-cus-and-is-codenamed-navi-12/

And I will quote:
I have also been told that Navi will be a new microarchitecture (in other words the first AMD Radeon uArch to not be based on GCN.

Navi is a codename. It is based on GCN. But the patents point to possibility that the execution of Instructions is different than before. And this is what everybody is saying about Navi, IMO, when they say it is different architecture than GCN.
 
Last edited:
Dec, what is even funier, the same WCCFTech site has posted this:

https://wccftech.com/exclusive-first-amd-navi-gpu-will-have-40-cus-and-is-codenamed-navi-12/

And I will quote:

Navi is a codename. It is based on GCN. But the patents point to possibility that the execution of Instructions is different than before. And this is what everybody is saying about Navi, IMO, when they say it is different architecture than GCN.

Different execution is pragmatically a different arch. (things like optimizers and other tools will require changes. )


1. Apple transitioned off of Imgination Tech GPU implementations by first doing the "back end " computational cores and then moving to the "front end" and the instruction decoders. Putting a new micro-arch back-end behind command decoders that take the "same stuff as before" is also largely how AMD went from there previous x86_64 implementation foundation to the Zen ones they are rolling out now. ( The high overlap in x86_64 instructions implemented by Zen implementations doesn't mean it is the same micro-architecture as before. )


2. The predecessor to GCN (graphics core next) was TeraScale. The former is a "RISC like SIMD " (single instruction multiple data ) basic approach. The TeraScale was far more so a VLIW (very long instruction word ) approach. So throwing out the instruction set made sense because the underlying core concept behind the approach was changing.

It is doubtful would switch back to VLIW or to something radically different. With all the GPGPU focus a RISC like instruction set with Vectors (and packed data , etc. ), there is demand for "general processor" opcodes. So unless there is something really quirky about the GCN instruction set like lack of reserved instruction space for new instructions ( probably not because it appears is a 2^12 space ) , excessively quirky state/control registers ( x86 gets by but...), undersized memory limits , register field limited restrictions on number of cores, etc. then they really don't have to completely throw the baby out with the bath water.

I think there is a notion that GCN was so "bad"/"disaster" that AMD was going to be required to completely throw everything out and start over from scratch including the baselines of the instruction set. I think that is a bit overblown. From a fast scan of the instruction set docs I don't think the 4096 sp limit is being driven by the instruction ( probably something about the internal "glue" ( crossbar, mesh , network ) that would be inherent to any implementation. Likely wise other stuff that is cache size ( LDS local data share will hit a cap at some point) , bandwidth , efficiency , power gating of subsections , etc. etc. completely boxed in by the instruction set either. In other words, very core level basic block for their function units was more in need of a revamp ( similar to getting Zen on a re-rationalized baseline for more that instruction set gymnastics. )


How many instruction set additions are required to justify a major name change? That depends. Going from 32 to 64 bits is obvious. There are some 64 bit instructions in GCN now. Perhaps if there are some useful 128 , 246 , 512 instruction to go with updates then they could easily justify a new name change. But there are other dimensions ( major new function units, major addressing changes , etc. )
[doublepost=1548625064][/doublepost]P.S. another example of AMD generically using 'Next' to mean the one after the current one. From their "teaser' slide deck for Vega back in very early 2017. The Compute Units in Vega ....... NCU Next-Generaiton Compute Unit.

Vega%20Final%20Presentation-27_575px.png


https://www.anandtech.com/show/11002/the-amd-vega-gpu-architecture-teaser/2


Which as about the new packed math capabilities. 8-bits ..... [ Vega 20 adds 4 bit ops so that would be the 'new' NGU of late 2018 - early 2019. ] AMD used the adjective 'Next' like pouring ketchup on a burger or hot dog.
 
Last edited:
If you are talking about instruction set, and GFX family name changes(Architectures).

Polaris was GFX 8 family, just like Tonga, Fiji, etc.

Vega, on the other hand was GFX 9 family. And it had Draw Stream Binning Rasterizer, High Bandwidth Cache Controller, and NCU's. And it was new architecture, alondside, new instructions, in the set.

The thing is: I don't believe AMD is going to shy away from GCN, from Instruction perspective. But the implementation of those GPUs will be vastly different.

Super-SIMD patent, and the patent for High Bandwidth Vector Register File(which basically means, that AMD has just Maxwell'ed their architectures) are pointing to this. This basic change may allow AMD to beyond simple 4 Shader Engine limit, without radical redesign of the implementation, and just allow AMD to stick just more Shader Engines, and Geometry Engines, at the same time to their architectures, to feed those cores properly.

The discussion in June last year, when the Patent of Super-SIMD was published was pointing to possibility that, AMD was looking for ways to reduce the memory bandwidth requirements, and at the same time - power draw of their GPUs, not on process level, but on Architectural Level. The other siede of this coin was pointing to a possibility that, saving Register File Bandwidth, saving power, will also allow AMD to increase core clocks, without changing to another node.

Current rumors point to a situation where RX 3080, based on Navi 10, a GPU that supposedly is smaller than Polaris 10(smaller than 232 mm2) is as fast as RTX 2070. The only way this would be possible is if the CUs have massively higher clock speeds, massively higher internal bandwidth, and massively higher Memory bandwith.
 
Register on MacRumors! This sidebar will go away, and you'll see fewer ads.