Damn, my first Computer was an i36SX (no Co-Processor) @ 25MHz. 12 MB Ram, 80 MB HDD. single speed CD-Rom connected to the Soundblaster via ATA. G4, G5,...
Times change.
Times change.
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Apple Books Nearly 90% of TSMC's 3nm Production Capacity for This Year
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Most of these was also true with 5nm and quite a while Apple was way ahead of anybody in terms of efficiency.
The are still "ahead" just not "way" anymore....
Sadly I wasn't joking
The issue is that due to constraints, snapdragon888 and 8 gen 2 sucked , because they couldn't use tsmc nodes and had to rely on Samsung fabrics ...which sucked. For 2 years...you know the story don't you. Terrible performance, heating , throttling like crazy . All that because they couldn't get tsmc nodes , and apple had all of 'em
Apart from Google that plans on keeping tensor with Samsung nodes for their Tensor G3 (if not more), there is demand for tsmc nodes .
Samsung and a LOT of other OEMs want it.
And SOC manufacturers do, too, namely Qualcomm, Mediatek, (Huawei's kirin too...but not sure about this one due to Huawei US ban...although tsmc have moved so idk)
3nm isn't a processor ,merely nodes
Every manufacturer has always been using 1st gen tsmc for years and years , i don't really understand what you mean
3nm does indeed represent a huge gap on price
Intel took a virtual monopoly and blew it. What are we to do? Its free enterprise. We cant have a double standard on capitalism and a free market. Should we give Intel government funded welfare and subsidies and hope they don’t continue to blow it or do we let the marketplace decide?
False. It's a choice. You get, according to TSMC, 30-35% better power or 15-20% better performance. Or lower boosts for both simultaneously.
Of course the reality won't match the IEDM slide perfectly. It depends on the specific chip.
See for example https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/, or the much more in depth and technical piece from semianalysis.
This information is way out of date. It's extremely unlikely they'll be using a 10-core chip(let) as a building block, when the M2 Pro/Max already uses 12 cores. It would be shocking if it were less than 12 cores, and unsurprising if it were 14 or 16.
False. The M2 is an 8-core CPU. The M2 Pro has either 10 or 12 cores, and the Max has 12.
Nothing will migrate to N3E. Future devices may well use N3E, especially the A18. But there's nothing like a "migration". N3E is not IP-compatible with N3B. Everything must be reimplemented.
HobeSoundDarryl
macrumors G5
Pffft! Mine was the great and mighty Commodore 64, making me computing king of my 'hood for a few months.
Check this out:
- 8-bit 1.023 Mhz CPU
- An unbelievable 64 Kilobytes of RAM. Yes 64K!!!
- Incredible 320 x 200 resolution with a gigantic pallete of 16 colors
- The Mighty SID 6581 sound chip which could make beep and boom sounds better than ANYTHING at the time
- No hard drive at all- who needed a hard drive?
- No CD-ROM at all- there was no such thing as CDs yet
Apple was years from Mac
PC was barely around, and no Windows for many years yet
Amiga was still incubating
Everybody wanted one.
And then the incredible 170Kb floppy drive came along so we could store an insane amount of data. 170 Kilobytes. OMG!
Ironically, now I'm dreaming about Apple basically making one of these- Apple thin & light- but basically the "whole computer" in a keyboard "case"- pretty much the bottom half of a MacBook now... to then be able to use with a virtualized, any-sized screen or screens in the rumored Googles.
Imagine an Apple version of C64 plus an any-sized monitor in the laptop bag... to be used much like we use laptops today... EXCEPT we finally have a MB17" or a MB18" or a MB20" or a MB24" or MB30" or MB50" or iMac 27" or 30" or 32", etc ALL in that laptop bag, ready to be used wherever we would pull out the cramped screen of an actual laptop.
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What makes the move to 3nm so different that companies don’t want to transition straight away when they have done so with previous transitions?
The issue is not with interest, it’s the high cost associated with this transition. Samsung have already transisitioned to 3nm partially and with Apple soon to follow others won’t be able to risk stagnating even with a contracting smartphone/computer market.
Oh those 80s... I didn't think anyone would win against me so easily. 👏
HobeSoundDarryl
macrumors G5
Easy! Wait until the Vic20 crowd shows up... or Spectrum... or Tandy... Atari 400 (look ma, no keys) or AppleII.
Some of them/us still have coherent thoughts... sometimes. 🤪
The dinosaurs didn't get all of us. But the cretaceous period was ROUGH!
Some of them/us still have coherent thoughts... sometimes. 🤪
The dinosaurs didn't get all of us. But the cretaceous period was ROUGH!
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Not true at all. M1/2 have 128-bit memory buses. Pros are 256b wide, Maxes are 512, and Ultras 1024. And yet, the M2 can be configured with 24GB. That's because the individual RAM packages are 12GB.
The power-of-two thing comes from RAM packaging.
How to make sense of the odd memory of 36GB?
I had some thoughts on the odd memory reported in the rumors, but it indeed seems to make sense, if you collect some facts.
The 3nm process will give roughly 30% increase in performance, not to count for gains of IPC etc. Logic shrinks considerably, perhaps 50% but SRAM cell size does not really decrease. So Apple can include more CPU and GPU cores but not efficiently increase cache memory. How to deal with this to feed the beast?
LPDDR prizes are significantly down. If I was Apple, I would increase the number of memory channels. You would roughly need a 50% increase of memory bandwidth to deal with the faster N3 process and more cores. The easiest way would to to go from 2 to 3 memory chips in the M3, and from 4 to 6 in the M3 pro. That would also work, as the connects would essentially take 3 of the four sides of the chip leaving the fourth for other I/0.
This would mean, RAM capacities would go up by 50% for all configurations, i.e. from 8 to 12 GB, from 16 to 24 and from 24 to 36. Voila, you have the strange 36 GB memory configuration in the base model (base CPU/GPU but maxed out memory).
This approach, of course, kills the die to die connection of the ultimate version and also the pro max would not fully scale (up from 8 to 10 channels would easily be possible).
Well, it is going to be interesting.....
I had some thoughts on the odd memory reported in the rumors, but it indeed seems to make sense, if you collect some facts.
The 3nm process will give roughly 30% increase in performance, not to count for gains of IPC etc. Logic shrinks considerably, perhaps 50% but SRAM cell size does not really decrease. So Apple can include more CPU and GPU cores but not efficiently increase cache memory. How to deal with this to feed the beast?
LPDDR prizes are significantly down. If I was Apple, I would increase the number of memory channels. You would roughly need a 50% increase of memory bandwidth to deal with the faster N3 process and more cores. The easiest way would to to go from 2 to 3 memory chips in the M3, and from 4 to 6 in the M3 pro. That would also work, as the connects would essentially take 3 of the four sides of the chip leaving the fourth for other I/0.
This would mean, RAM capacities would go up by 50% for all configurations, i.e. from 8 to 12 GB, from 16 to 24 and from 24 to 36. Voila, you have the strange 36 GB memory configuration in the base model (base CPU/GPU but maxed out memory).
This approach, of course, kills the die to die connection of the ultimate version and also the pro max would not fully scale (up from 8 to 10 channels would easily be possible).
Well, it is going to be interesting.....
I wonder if the 3nm chip is not in fact for the RealityPro instead of the Mac (which only recently got updated to M2). The key benefit of 3nm would be computer vs power consumption and I would think the headset would need that the most.
They make decisions on what foundry to use up front, when they’re planning the chip. If they didn’t use TSMC it’s because they didn’t contract with TSMC up front. That has nothing to do with Apple, but I’m sure there are those that would like to punish Apple for their ability to plan and make decisions of which foundry will produce chips up front. OR, punish Apple for their ability pay enough to TSMC such that TSMC can build new capacity in order to fulfill their orders both now and in the future. TSMC, is just a company looking to make a buck, so if a company has the bucks, TSMC will find a way to take their money.
No, they don’t.
Major TSMC Customers Cancel 3nm Chip Orders while the company Settles on 1nm Plant Location
It's being reported this morning in Taiwan that TSMC was affected by the temporary cancellation of orders by 3nm customers
Major TSMC Customers Cancel 3nm Chip Orders while the company Settles on 1nm Plant Location
It's being reported this morning in Taiwan that TSMC was affected by the temporary cancellation of orders by 3nm customers
This is repeatedly stated in a misleading and inaccurate way here on MR. There are two, orthogonal statements here that describe the process improvement in different ways:
1. 35% lower power for the same performance
2. 15% greater performance at the same power
Once you state it correctly, clearly you can't call 15% greater performance at the same power a '35% power efficiency improvement'. You can have 35% greater efficiency at the same performance, OR you can have 15% more performance at a lesser efficiency advantage. You don't get to have both.
They weren’t cancelled because they didn’t want 3nm like you claimed. They were cancelled because verification and design issues. That plus production not being at full capacity paired with Apple taking up most of that capacity and weakness in the market has meant they had no choice but to delay in when they rollout, with many saying early 2024. They’re looking to implement WHEN capacity allows and have resolved design issues.I don’t know, ask those companies that canceled orders last year why they’re not interested in 3nm node processors?
Major TSMC Customers Cancel 3nm Chip Orders while the company Settles on 1nm Plant Location
It's being reported this morning in Taiwan that TSMC was affected by the temporary cancellation of orders by 3nm customerswww.patentlyapple.com
While there might be some cases where that's true, mostly nobody wants the N3B process because it's expensive! Design cost is higher, and unlike previous next-gen nodes, cost per transistor isn't meaningfully less (and might be more). Apple is willing to pay the price, and others aren't. Everyone other than Apple is waiting for N3E, which costs less per transistor despite being slightly/somewhat less dense due to simplified process (and, relatedly, better expected yield).
I again refer you to the link I posted above, and the semianalysis article I mentioned.
The unlikely characterization is dependent upon Apple brute forcing the Max into a chiplet role at the M3 stage. The Max is not really a good chiplet design. It is bit too chunky, dubious lack of function decomposition when it comes to scaling past two die, and lots of laptop monolithic baggage. It doesn't scale well. Apple could do a good chiplet design. AMD's desktop/server chiplets have 8 cores. There would be absolutely nothing wrong with just 10 ( two 4 core P clusters and a chopped down 2E cluster ). If always use at least two chiplets in package then the number of CPU cores will outnumber the M2/M3 Max. ( 20 vs 12 CPU).
If want to get to 2, 3, 4 chiplets than then will get CPU (and GPU ) core count scale with the additional chiplets. The baseline design parameters are trying to stuff a high count onto a single die to fanatically maximize perf/watt.
If these are desktop Mac system only packages why try to hit the thermal envelope limitations of the MBP 14"? That doesn't make much sense. Apple doesn't have to throw Perf/Watt completely out the windows but UltraFusion is costing Perf/Watt also. It is useful to let go of fanatical stance slightly at some point if it gets them some upsides in the desktop context.
If Apple forgoes the full E core package to goose out some extra GPU cores , there is a pretty good chance that many desktop folks will take that trade off. Even more so if give them some single threaded drag racing perks. So even a one chiplet setup wouldn't necessarily be a 'looser'.
so if just had two chiplets:
[ I/O die ] thunderbolt , SSD, Security Enclave , PCI-e , ( and maybe display controllers and/or video en/decode ) can leave at N5P or N4P , UltraFusion on one side.
[ CPU/GPU/Memory/NPU SLC] 10 CPU 40 GPU Memory controllers goes to N3 ( and future target N2 family). UlraFusion on top/bottom.
then could get 4 packages .
10 CPU 40 GPU < mac studio >
[ I/O die ]
[ CPU/ GPU ]
20 CPU 80 GPU < mac studio , mac pro >
[ I/O die ]
[ CPU / GPU ]
[ CPU / GPU ]
[ I/O die ]
30 CPU 120 GPU < mac pro >
[ I/O die ]
[ CPU / GPU ]
[ CPU / GPU ]
[ CPU / GPU ]
[ I/O die ]
40 CPU 160 GPU < mac pro >
[ I/O die ]
[ CPU / GPU ]
[ CPU / GPU ]
[ CPU / GPU ]
[ CPU / GPU ]
[ I/O die ]
And apple could retire the "Max" from pretending to be a chiplet when it really isn't. If the 4 'cores' chiplet stack has some top to bottom distance problems then chop GPU cores out and make the chiplets smaller (they'll get more affordable and have higher yields. ). .
The N5 fab process used for the M1 doesn't have the same non-scalling factors that n3 has. So why should be chiplet subunit clustering strategy be fixed in stone based on N5 presumptions when you get the N3 and N2? That doesn't make sense. Minimally, it changes the likelihoods on keeping the core counts down being better.
So, they canceled them because, at the quality TSMC was making, they didn’t meet those companies goals? So… they… don’t… want… what… TSMC… produces… at… 3… nm?
AND, further, if those companies DID want what TSMC was producing, if there WEREN’T issues, then they would have placed orders for products and maintained orders for current products… which would mean Apple’s 90% would be considerably less. Apple hasn’t PREVENTED them from placing orders, TSMC’s inability to provide them with a product that met their goals prevented them from placing orders.
