We need a 2 nm battery. Not much progress on that front.The circuit boards will be so small that surely Apple will be able to reissue the iPhone mini.
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Apple Partner TSMC Unveils Advanced 1.6nm Process for 2026 Chips
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Depending on how define your measurement you can expect a battery life of a few picoseconds I reckon.
This is misleading. The 45 nm process had a gate pitch of 160 nm, and the 2 nm and 1 nm processes have a predicted gate pitch of 45 and 42 nm, respectively. In that measure, it’s a reduction to 35–38 % over 16-ish years, which is still impressive, but less unexpected.
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I doubt it. Since these numbers apparently are just based on marketing, and not physics, then we have no way to say how much these chips really shrank.
Could work, or we just can move on to the next name in the scale. Introducing the Picometer.
The measurement system that this site has to leave behind is imperial, and stays in the rational metric system—the one that the whole world uses, except the USA and two little islands.
Process dimensions are only one metric... there are so many other ways they can move forward
Process shrinkage was actually an easy way to advance designs... except for the manufacturing angle.
Process shrinkage was actually an easy way to advance designs... except for the manufacturing angle.
So how small will things go until an errant cosmic ray can brick your iPhone? 🤪
Oh no, we can’t do that. 16 is a larger number than 1.6 so less (shall we say) attentive readers would think the new chip is actually BIGGER rather than smaller than the current one. Marketing would have a cow. 🤡
Do you think Intel will hit those targets? And are they measuring these the same way?
Technically true, but my recollection is that speculation and predictions back then were much more dire than simply "slows down a bit".
It's kind of funny that Apple is now in a similar situation to where Intel has been... beholden to process shrinks in order to achieve generational gains. They can still do "tock" updates but ultimately, as TSMC goes so goes Apple.
This is a genuine concern for space bound hardware. Scrubbing and error checking are paramount
We already are at a fairly rigid wall, so it's happening right now. It will just get more and more difficult to make newer nodes each time. The massive increase in density mentioned is ~10% for this node. Not really massive, but still impressive at this scale regardless. Some components haven't been able to shrink in a while now (memory is a good example).
Yeah, most likely you'll have to convert that to "Intel Time", which means adding 3 years to each announced target date.
It’s one of the reasons why modern space probes and Mars rovers still mostly use variants of PowerPC G3 CPU’s.
"This development is expected to provide an 8-10% increase in speed and a 15-20% reduction in power consumption at the same speeds compared to TSMC's N2P process, alongside up to a 1.10x chip density improvement."
I'm not sure this is correct.
The 2023 plan was that N2 was about GAA, and N2P was about adding BSPD.
What seems to be new is a relabelling, what was going to be called N2P is now going to be called A16.
This is a justifiable change, IMHO, in that adding BSPD is a large enough improvement that a new "half-node" name is justified.
(Which won't, of course, stop the usual crowd from telling us, the same way they have told us for 10+ years now, that the node name is unjustified, it's "lying", there is nothing on the chip sized at 16A, etc etc. Like this is some sort of news no-one knows, where the only real ignorance is that these people STILL, after ten year, dom't understand how node-naming works - and refuse to learn.)
I'm not sure this is correct.
The 2023 plan was that N2 was about GAA, and N2P was about adding BSPD.
What seems to be new is a relabelling, what was going to be called N2P is now going to be called A16.
This is a justifiable change, IMHO, in that adding BSPD is a large enough improvement that a new "half-node" name is justified.
(Which won't, of course, stop the usual crowd from telling us, the same way they have told us for 10+ years now, that the node name is unjustified, it's "lying", there is nothing on the chip sized at 16A, etc etc. Like this is some sort of news no-one knows, where the only real ignorance is that these people STILL, after ten year, dom't understand how node-naming works - and refuse to learn.)
That is the best take on the current naming scheme: no relation to physical features.
The most plausible proposed explanation I've seen for it is:
IF they still used a planar process, which they do not, it would require features of that size to achieve the same density.
They are, that is why TSMC is calling the process A16 (the A is for Angstroms).
Great question. Regarding the first question, I’ll bet the schedule eventually slips by a year. Regarding the second question, Intel changed their naming to line up with TSMC, so I suspect it is measured in about the same way.
My confidence in Intel has increased since Gelsinger returned. Intel finally got Intel 7 out the door and then Intel 4. So they are showing competence again.
Another question is volume— how much can they produce? And I bet they will be capacity constrained for a while. Maybe they could produce the M lineup, but probably not the A.
Probably is correct. Basically taken from the TSMC press release. Following is TSMC graphic (see copyright on the photo) .
TSMC unveils 1.6nm process technology with backside power delivery, rivals Intel's competing design
TSMC goes angstrom-class nodes.
TSMC is being cautious. They are doing GAA without backside first (N2). Then applying only backside ( N2P) . And only then going to push harder for more density ( I think this is when they are transitioning to High NA EUV fab machines. ). Just doing one substantive change at a time reduces risk. N2P is going to be relaxed enough so they don't run into too many multipatterning problems ( similar to N3E versus N3B) .
There is 20% drop from 20 to 16 but only really getting, at best, 10% . It is getting more and more marketing numbers to cover up the slower ( and increasingly more expensive) changes. The only 20% can hand wave at is the power reduction. ( which will get same speed as last gen ... so how many HPC designers are going to choose that? )
Correct. 3nm does not mean each transistor is 3nm wide. "3nm" is a marketing term.
Probably is correct. Basically taken from the TSMC press release. Following is TSMC graphic (see copyright on the photo) .
![mjEGKugAM7DPXKGJuqdneK-1200-80.png]()
TSMC unveils 1.6nm process technology with backside power delivery, rivals Intel's competing design
TSMC goes angstrom-class nodes.www.tomshardware.com
TSMC is being cautious. They are doing GAA without backside first (N2). Then applying only backside ( N2P) . And only then going to push harder for more density ( I think this is when they are transitioning to High NA EUV fab machines. ). Just doing one substantive change at a time reduces risk. N2P is going to be relaxed enough so they don't run into too many multipatterning problems ( similar to N3E versus N3B) .
There is 20% drop from 20 to 16 but only really getting, at best, 10% . It is getting more and more marketing numbers to cover up the slower ( and increasingly more expensive) changes. The only 20% can hand wave at is the power reduction. ( which will get same speed as last gen ... so how many HPC designers are going to choose that? )
Look at the dates.
2H 2026 is when N2P was supposed to ship. BSPD is the headline feature that was supposed to be added to N2P.
The improvements are all inline (relative to N2) with what N2P was expected to deliver.
Below was the roadmap in 2023. The point is how it has changed as of 2024.
You're not fully understanding what's going on here.
- A16 does not use high-NA EUV.
TSMC A14 probably will, but I don't know if that's been confirmed yet
- BSPD requires somewhat more rethinking of chip layout than many previous node improvements (for example I've seen some Apple patents for alternative SRAM cache layouts that exploit BSPD). My guess is that some customers told TSMC that, rather than having the next upgrade to N2 (ie N2P) based on BSPD, they'd prefer an "easy" optical-shrink-style upgraded node, with BSPD placed on a different track, one that requires a new design rather than a slightly updated design.
ie this is not about "failure" or "slowing down", it's about TSMC being responsive to customers, the same attitude that got them to number one, and that keeps them there. Same reason that there's a "Mainstream" TSMC track with nodes like N4P and N3P that are "easy" upgrades for existing customer designs.
I don't think we can be at all sure just how much density boost BSPD can deliver, in part because it depends on how aggressively chips are redesigned, and in part on how aggressively TSMC is willing to add more backside metal layers.
Obviously moving power to the backside relieves some wiring congestion, which in turn allows for denser SRAM.
You can then also move clock to the backside and remove more congestion – but can you do that with TSMC's first version of the tech? Quite possibly not; it's standard TSMC practice to add just one thing at a time and refine it each year, not to add the full range of possibilities at once. Same thing for at least certain types of signal data.
And please spare us the editorial commentary on how these improvements are all marketing, they aren't real, they're too expensive, blah, blah. These complaints were boring when they were applied to N14 and they're even more boring ten years later.
You'd think people repeating the same damn thing (and being wrong) every year would learn something, but apparently not...
Would you accept transistor count as a proxy? While it doesn’t directly speak to chip “shrinkage” it does somewhat speak to chip density as I don’t believe the SOC physical dimensions have changed significantly. If so, transistor count has more than doubled from A13 Bionic (released September 2019 and having 8.5 billion) to A17 Pro (released September 2023 and having 19 billion transistors). With that as a metric, that’s a pretty impressive 100%+ “improvement” in 4 years.