I’m all for integrating as much as possible onto an Apple Silicon die, but might it not be better to use an “off die” PCI controller IC? Macs and Apple devices are trapped for years with whatever version of PCI Apple integrated into their latest Apple Silicon SIP/SoC.
It could be 'off die' but it would still be inside of Apple's package. Amazon's Graviton 3 doesn't put the PCI-e or Memory controllers on the "compute" die.
https://www.nextplatform.com/2022/01/04/inside-amazons-graviton3-arm-server-processor/
Amazon AWS Graviton3 C7g instances are now in GA and are built upon a 3 CPU per motherboard design which is very unique
www.servethehome.com
AMD did a different disaggregation where they took the memory and L3 cache off and left the PCIe and displayPort output on the main die.
IMHO, Apple does need a better chiplet design strategy for desktop ( minimally the Studio , Mac Pro and perhaps a large screen iMac with performance ) that laptops probably won't want to use. A 'desktop' Max , Ultra (which only will ever be desktop) , and a > 2 compute chiplet "extreme".
Replicating past 6 Thunderbolt controllers gets into the certifiably silly zone. Past 4 is dubious. The Mac Studio putting 1 or 2 on the front is useful if doing a decent amount of plug/unplug activity (instead of reaching around the back). So there is small "get out of silly jail" card there. Multiple secure elements , SSD controllers are relatively silly to once get past two 'chiplets'. The Max die is a relatively too chunky 'chiplet'.
Also, it doesn't make tons of sense to put the general I/O functionality on TSMC N3 (and better ) either because the off package external communication lanes are not going to scale well either. So they cost more for no good reason. Sooner or later Apple will probably decouple a subsection with PCI-e in it from the compute cores. I doubt Apple will decoupled the CPU/NPU/GPU cores from one another though. (i.e. Apple start making CPU-less or GPU-less packages). Very long term it is probably coming. Is is coming for M2 generation. Not sure.
And a long and costly Silicon redesign is required just to bump up the supported PCI version/standard/protocol.
Conceptually Apple could buy an baseline PCI-e controller design 'off-the-shelf' but with CXL it needs to integrated with the internal cache coherency implementation is. Unless there is some huge security model and coherency model mismatch between Apple's internals and the standard PCI-e + CXL external model, that shouldn't be ridiculously expensive.
It is more lane bundle breadth that I think will be more a problem with Apple than them moving along the basic PCI-e vN upgrade train. I suspect they'd like to feed just one x16 PCI-e v5 bundle to a PLEX PCI-e switch to dole out 8 PCI-e v3 lanes worth of slots than to do two x16 PCI-e v4 lanes (and shrinking back from the Intel W-3200 64 PCI-e v3 lanes). Chasing wider , aggregate LPDDRx memory lanes just being a higher priority. Move the PCI-e data off the package and then "expand" it by branching out.
Faster Wi-Fi modules are coming too ( WiFI 7 and whatever else follows. So point connections will trickle down the rest of Mac line up also. )
The 'cost' problem is more so that they are not going to sell relatively many "Mac Pro only" PCI-e controllers if they try to chase after the upper bleeding edge going forward ( chasing PCI-e v6 in same 18-month window as server SoCs from Amazon , Intel, AMD will. ) They just are not going to make that many as those other players.
wccftech.com
